DS90CR483A_15 Datasheet, PDF (15/27 Pages) Texas Instruments – 48-Bit LVDS Channel Link SER/DES - 33 - 112 MHz

DS90CR483A, DS90CR484A
www.ti.com
SNLS291A – APRIL 2008 – REVISED APRIL 2013
HOW TO CONFIGURE FOR BACKPLANE APPLICATIONS
In a backplane application with differential line impedance of 100Ω the differential line pair-to-pair skew can
controlled by trace layout. The transmitter-DS90CR483A “DS_OPT” pin may be set high. In a backplane
application with short PCB distance traces, pre-emphasis from the transmitter is typically not required. The “PRE”
pin should be left open (do not tie to ground). A resistor pad provision for a pull up resistor to Vcc can be
implemented in case pre-emphasis is needed to counteract heavy capacitive loading effects.
HOW TO CONFIGURE FOR CABLE INTERCONNECT APPLICATIONS
In applications that require the long cable drive capability. The DS90CR483A/DS90CR484A chipset is improved
over prior generations of Channel Link devices and offers higher bandwidth support and longer cable drive with
the use of DC balanced data transmission, pre-emphasis. Cable drive is enhanced with a user selectable pre-
emphasis feature that provides additional output current during transitions to counteract cable loading effects.
This requires the use of one pull up resistor to Vcc; please refer to Electrical Characteristics to set the level
needed. Optional DC balancing on a cycle-to-cycle basis, is also provided to reduce ISI (Inter-Symbol
Interference) for long cable applications. With pre-emphasis and DC balancing, a low distortion eye-pattern is
provided at the receiver end of the cable. These enhancements allow cables 5+ meters in length to be driven.
Depending upon clock rate and the media being driven, the cable Deskew feature may also be employed - see
discussion on DESKEW, RSKM and RSKMD above.
SUPPLY BYPASS RECOMMENDATIONS
Bypass capacitors must be used on the power supply pins. Different pins supply different portions of the circuit,
therefore capacitors should be nearby all power supply pins except as noted in the pin description table. Use
high frequency ceramic (surface mount recommended) 0.1µF capacitors close to each supply pin. If space
allows, a 0.01µF capacitor should be used in parallel, with the smallest value closest to the device pin. Additional
scattered capacitors over the printed circuit board will improve decoupling. Multiple (large) via should be used to
connect the decoupling capacitors to the power plane. A 4.7 to 10 µF bulk cap is recommended near the
PLLVCC pins and also the LVDSVCC (pin #40) on the Transmitter. Connections between the caps and the pin
should use wide traces.
INPUT SIGNAL QUALITY REQUIREMENTS - TRANSMITTER
The input signal quality must comply to the datasheet requirements, please refer to the "Recommended
Transmitter Input Characteristics" table for specifications. In addition undershoots in excess of the ABS MAX
specifications are not recommended. If the line between the host device and the transmitter is long and acts as a
transmission line, then termination should be employed. If the transmitter is being driven from a device with
programmable drive strengths, data inputs are recommended to be set to a weak setting to prevent transmission
line effects. The clock signal is typically set higher to provide a clean edge that is also low jitter.
UNUSED LVDS OUTPUTS
Unused LVDS output channels should be terminated with 100 Ohm at the transmitter’s output pin.
RECEIVER OUTPUT DRIVE STRENGTH
The DS90CR484A output specify a 8pF load, V_OH and V_OL are tested at ± 2mA, which is intended for only 1 or
maybe 2 loads. If high fan-out is required or long transmission line driving capability, buffering the receiver output
is recommended. Receiver outputs do not support / provide a TRI-STATE function.
Copyright © 2008–2013, Texas Instruments Incorporated
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