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DS90CR483A_15 Datasheet, PDF (18/27 Pages) Texas Instruments – 48-Bit LVDS Channel Link SER/DES - 33 - 112 MHz
DS90CR483A, DS90CR484A
SNLS291A – APRIL 2008 – REVISED APRIL 2013
www.ti.com
Pin Name
RxINP
RxINM
RxOUT
RxCLKP
RxCLKM
RxCLKOUT
PLLSEL
DESKEW
PD
VCC
GND
PLLVCC
PLLGND
LVDSVCC
LVDSGND
NC
DS90CR484A Pin Descriptions—Channel Link Receiver(1)
I/O
Description
I
Positive LVDS differential data inputs.
I
Negative LVDS differential data inputs.
O
TTL level data outputs. In PowerDown (PD = Low) mode, receiver outputs are forced to a Low
state.
I
Positive LVDS differential clock input.
I
Negative LVDS differential clock input.
O
TTL level clock output. The rising edge acts as data strobe.
I
PLL range select. This pin should be tied to VCC for high-range. Tied to ground or NC will force the
PLL to low range only. Low range is 33 — 40 MHz. High range is 38 — 112 MHz.(2)
I
Deskew / Oversampling “on/off” select. When using the Deskew / Oversample feature this pin
must be tied to VCC. Tieing this pin to ground disables this feature. (2) Deskew is only supported in
the DC Balance mode.
I
TTL level input. When asserted (low input) the receiver outputs are Low. (2)
I
Power supply pins for TTL outputs and digital circuitry. Bypass not required on Pins 6 and 77.
I
Ground pins for TTL outputs and digital circuitry.
I
Power supply for PLL circuitry.
I
Ground pin for PLL circuitry.
I
Power supply pin for LVDS inputs.
I
Ground pins for LVDS inputs.
No Connect. Make NO Connection to these pins - leave open.
(1) These receivers have input fail-safe bias circuitry to ensure a stable receiver output for floating or terminated receiver inputs. Under test
conditions receiver inputs will be in a HIGH state. If the cable interconnect (media) are disconnected which results in floating/terminated
inputs, the outputs will remain in the last valid state.
(2) Inputs default to “low” when left open due to internal pull-down resistor.
18
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