DS90CR483A_15 Datasheet, PDF (5/27 Pages) Texas Instruments – 48-Bit LVDS Channel Link SER/DES - 33 - 112 MHz

DS90CR483A, DS90CR484A
www.ti.com
SNLS291A – APRIL 2008 – REVISED APRIL 2013
Recommended Transmitter Input Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Min
Typ
TCIT
TxCLK In Transition Time (Figure 4)
1.0
2.0
TCIP High TxCLK In Period, PLLSEL = High Gear (Figure 5)
8.928
T
TCIP Low TxCLK In Period, PLLSEL = Low Gear (Figure 5)
25
T
TCIH
TxCLK In High Time (Figure 5)
0.35T
0.5T
TCIL
TxCLK In Low Time (Figure 5)
0.35T
0.5T
TXIT
TxIN Transition Time
1.5
Max
3.0
26.3
30.3
0.65T
0.65T
6.0
Units
ns
ns
ns
ns
ns
ns
Transmitter Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Min
Typ
LLHT
LVDS Low-to-High Transition Time, (Figure 2),
0.14
PRE = 0.75V (disabled)
LVDS Low-to-High Transition Time, (Figure 2),
0.11
PRE = Vcc (max)
LHLT
LVDS High-to-Low Transition Time, (Figure 2),
0.16
PRE = 0.75V (disabled)
LVDS High-to-Low Transition Time, (Figure 2),
0.11
PRE = Vcc (max)
TBIT
Transmitter Bit Width
1/7 TCIP
TPPOS Transmitter Pulse Positions -
f = 33 to 70 MHz
−250
0
Normalized
f = 70 to 112 MHz
−200
0
TJCC
Transmitter Jitter - Cycle-to-Cycle⁽¹⁾
50
TCCS
TxOUT Channel to Channel Skew
40
TSTC
TxIN Setup to TxCLK IN, (Figure 5)
2.5
THTC
TxIN Hold to TxCLK IN, (Figure 5)
0
TPDL
Transmitter Propagation Delay - Latency, (Figure 7)
1.5(TCIP)+3.72 1.5(TCIP)+4.4
TPLLS Transmitter Phase Lock Loop Set, (Figure 9)
TPDD
Transmitter Powerdown Delay, (Figure 11)
Max
Units
0.7
ns
0.6
ns
0.8
ns
0.7
ns
ns
+250
ps
+200
ps
100
ps
ps
ns
ns
1.5(TCIP)+6.24
ns
10
ms
100
ns
(1) TJCC is a function of input clock quality and also PLLVCC noise. At 112MHz operation, with a +/−300ps input impulse at a 2us rate,
TJCC has been measured to be in the 70-80ps range (<100ps). With a nominal input clock quality (no input impulse jitter, jitter <
500kHz), TJCC is typically 50ps or less. For RSKM/RSKMD calculations 100ps is typically used as the TJCC budget. See Clock Jitter
discussion in the Applications Information section of this datasheet for further information.
Receiver Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Min
Typ
CLHT
CMOS/TTL Low-to-High Transition Time, (Figure 3), Rx
data out
CMOS/TTL Low-to-High Transition Time, (Figure 3), Rx
clock out
CHLT
CMOS/TTL High-to-Low Transition Time, (Figure 3), Rx
data out
CMOS/TTL High-to-Low Transition Time, (Figure 3), Rx
clock out
RCOP
RxCLK OUT Period, (Figure 6)
8.928
T
RCOH
RxCLK OUT High Time, (Figure 6)⁽¹⁾ f = 112 MHz
3.5
f = 66 MHz
6.0
Max
Units
2.0
ns
1.0
ns
2.0
ns
1.0
ns
30.3
ns
ns
ns
(1) The Minimum and Maximum Limits are based on statistical analysis of the device performance over voltage and temperature ranges.
This parameter is functionally tested on Automatic Test Equipment (ATE). ATE is limited to 85MHz. A sample of characterization parts
have been bench tested to verify functional performance.
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