DS90CR483A_15 Datasheet, PDF (12/27 Pages) Texas Instruments – 48-Bit LVDS Channel Link SER/DES - 33 - 112 MHz

DS90CR483A, DS90CR484A
SNLS291A – APRIL 2008 – REVISED APRIL 2013
www.ti.com
APPLICATIONS INFORMATION
The DS90CR483A and DS90CR484A are upgrades to the DS90CR483 and DS90CR484. The
DS90CR483A/DS90CR484A no longer have a PLL auto gear option selectable via the PLLSEL pin. The PLLSEL
pin now allows for the PLL low gear only or high gear only to be selected. The DS90CR483A/DS90CR484A are
fully compatible with older generation Channel Link devices. It should be noted that whenever devices with the
auto gear feature are used, an unintentional gear shift caused by fluctuations in V_CC may cause bit errors. By
removing the auto gear feature in the DS90CR483A/DS90CR484A, the potential for any gear shift related bit
errors has been eliminated.
The DS90CR483A/DS90CR484A chipset is improved over prior generations of Channel Link devices and offers
higher bandwidth support and longer cable drive with three areas of enhancement. To increase bandwidth, the
maximum clock rate is increased to 112 MHz and 8 serialized LVDS outputs are provided. Cable drive is
enhanced with a user selectable pre-emphasis feature that provides additional output current during transitions to
counteract cable loading effects. This requires the use of one pull up resistor to Vcc; please refer to Table 1 to
set the level needed. Optional DC balancing on a cycle-to-cycle basis, is also provided to reduce ISI (Inter-
Symbol Interference). With pre-emphasis and DC balancing, a low distortion eye-pattern is provided at the
receiver end of the cable. A cable deskew capability has been added to deskew long cables of pair-to-pair skew
of up to ±1 LVDS data bit time (up to 80 MHz clock rates). For details on deskew, refer to “Deskew” section
below. These three enhancements allow cables 5+ meters in length to be driven depending upon media and
clock rate.
The DS90CR483A/DS90CR484A chipset may also be used in a non-DC Balance mode. In this mode pre-
emphasis is supported. In this mode, the chipset is also compatible with 21 and 28-bit Channel Link Receivers.
See LVDS Interface for the LVDS mapping.
NEW FEATURES DESCRIPTION
1. Pre-emphasis
Pre-emphasis adds extra current during LVDS logic transition to reduce the cable loading effects. Pre-emphasis
strength is set via a DC voltage level applied from min to max (0.75V to Vcc) at the “PRE” pin. A higher input
voltage on the ”PRE” pin increases the magnitude of dynamic current during data transition. The “PRE” pin
requires one pull-up resistor (Rpre) to Vcc in order to set the DC level. There is an internal resistor network,
which cause a voltage drop. Please refer to the tables below to set the voltage level.
The waveshape at the Receiver input should not exhibit over or undershoot with the proper amount of pre-
emphasis set. Too much pre-emphasis generates excess noise and increases power dissipation. Cables less
than 2 meters in length typically do not require pre-emphasis.
Rpre
1MΩ or NC
50kΩ
9kΩ
3kΩ
1kΩ
100Ω
Table 1. Pre-emphasis DC voltage level with (Rpre)
Resulting PRE Voltage
0.75V
1.0V
1.5V
2.0V
2.6V
Vcc
Effect
Standard LVDS
50% pre-emphasis
100% pre-emphasis
12
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