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MSP430FR573 Datasheet, PDF (64/109 Pages) Texas Instruments – MIXED SIGNAL MICROCONTROLLER
MSP430FR573x
MSP430FR572x
SLAS639D – JULY 2011 – REVISED AUGUST 2012
10-Bit ADC, Power Supply and Input Range Conditions
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
AVCC
V(Ax)
IADC10_A
Analog supply voltage
Analog input voltage range
Operating supply current into
AVCC terminal, reference
current not included
AVCC and DVCC are connected together,
AVSS and DVSS are connected together,
V(AVSS) = V(DVSS) = 0 V
All ADC10 pins
fADC10CLK = 5 MHz, ADC10ON = 1,
REFON = 0, SHT0 = 0, SHT1 = 0,
ADC10DIV = 0
CI
Input capacitance
Only one terminal Ax can be selected at one
time from the pad to the ADC10_A capacitor
array including wiring and pad
RI
Input MUX ON resistance
AVCC ≥ 2 V, 0 V ≤ VAx ≤ AVCC
10-Bit ADC, Timing Parameters
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
fADC10CLK
For specified performance of ADC10 linearity
parameters
fADC10OSC
Internal ADC10 oscillator
(MODOSC)
ADC10DIV = 0, fADC10CLK = fADC10OSC
tCONVERT Conversion time
REFON = 0, Internal oscillator,
12 ADC10CLK cycles, 10-bit mode,
fADC10OSC = 4.5 MHz to 5.5 MHz
External fADC10CLK from ACLK, MCLK, or SMCLK,
ADC10SSEL ≠ 0
tADC10ON
Turn on settling time of
the ADC
The error in a conversion started after tADC10ON is
less than ±0.5 LSB,
Reference and input signal already settled
tSample
Sampling time
RS = 1000 Ω, RI = 36000 Ω, CI = 3.5 pF,
Approximately eight Tau (τ) are required to get an
error of less than ±0.5 LSB
(1) 12 × ADC10DIV × 1/fADC10CLK
10-Bit ADC, Linearity Parameters
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
EI
Integral
linearity error
ED
Differential
linearity error
1.4 V ≤ (VeREF+ – VREF–/VeREF–)min ≤ 1.6 V
1.6 V < (VeREF+ – VREF–/VeREF–)min ≤ VAVCC
(VeREF+ – VREF–/VeREF–)min ≤ (VeREF+ – VREF–/VeREF–)
EO
Offset error
(VeREF+ – VREF–/VeREF–)min ≤ (VeREF+ – VREF–/VeREF–)
Gain error, external
reference
(VeREF+ – VREF–/VeREF–)min ≤ (VeREF+ – VREF–/VeREF–)
EG
Gain error, internal
reference (1)
Total unadjusted
error, external
(VeREF+ – VREF–/VeREF–)min ≤ (VeREF+ – VREF–/VeREF–)
reference
ET
Total unadjusted
error, internal
reference (1)
(1) Error is dominated by the internal reference.
VCC
2V
3V
2.2 V
VCC
2 V to
3.6 V
2 V to
3.6 V
2 V to
3.6 V
2 V to
3.6 V
2V
3V
VCC
2 V to
3.6 V
2 V to
3.6 V
2 V to
3.6 V
2 V to
3.6 V
2 V to
3.6 V
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MIN TYP MAX UNIT
2.0
3.6 V
0
AVCC V
90 140
µA
100 160
6
8 pF
36 kΩ
MIN TYP MAX UNIT
0.45
5 5.5 MHz
4.5 4.5 5.5 MHz
2.18
2.67
µs
(1)
100 ns
1.5
µs
2.0
MIN TYP MAX UNIT
-1.4
1.4
LSB
-1.1
1.1
-1
1 LSB
-6.5
6.5 mV
-1.2
1.2 LSB
-4
4%
-2
2 LSB
-4
4%
64
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