MSP430FR573 Datasheet, PDF (12/109 Pages) Texas Instruments – MIXED SIGNAL MICROCONTROLLER

MSP430FR573x
MSP430FR572x
SLAS639D – JULY 2011 – REVISED AUGUST 2012
Functional Block Diagram –
MSP430FR5720IPW, MSP430FR5724IPW, MSP430FR5728IPW,
MSP430FR5730IPW, MSP430FR5734IPW, MSP430FR5738IPW
PJ.4/XIN PJ.5/XOUT
DVCC DVSS VCORE AVCC AVSS
PA
P1.x P2.x
Clock
System
ACLK
SMCLK
16 KB
(’5738, ’5728)
8 KB
(’5734, ‘5724)
4 KB
(’5730, ‘5720)
MCLK
FRAM
Memory
Protection
Unit
CPUXV2
and
Working
Registers
MAB
MDB
1 KB
RAM
Boot
ROM
Power
Management
SVS
SYS
Watchdog
REF
I/O Ports
P1/P2
1×8 I/Os
1×7 I/Os
Interrupt
& Wakeup
PA
1×15 I/Os
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DMA
3 Channel
RST/NMI/SBWTDIO
TEST/SBWTCK
PJ.0/TDO
PJ.1/TDI/TCLK
PJ.2/TMS
PJ.3/TCK
EEM
(S: 3+1)
JTAG/
SBW
Interface
MPY32
TA0
TB0
TA1
(2) Timer_A (1) Timer_B
3 CC
3 CC
Registers Registers
RTC_B
CRC
eUSCI_A0:
UART,
IrDA, SPI
eUSCI_B0:
SPI, I2C
ADC10_B
10 Bit
200KSPS
Comp_D
12 channels
12 channels
(8 ext/2 int)
Functional Block Diagram –
MSP430FR5722IPW, MSP430FR5726IPW,
MSP430FR5732IPW, MSP430FR5736IPW
PJ.4/XIN PJ.5/XOUT
DVCC DVSS VCORE AVCC AVSS
Clock
System
ACLK
SMCLK
16 KB
(’5736, ’5726)
8 KB
(’5732, ‘5722)
MCLK
FRAM
Memory
Protection
Unit
CPUXV2
and
Working
Registers
MAB
MDB
1 KB
RAM
Boot
ROM
Power
Management
SVS
SYS
Watchdog
PA
P1.x P2.x
I/O Ports
P1/P2
1×8 I/Os
1×7 I/Os
Interrupt
& Wakeup
PA
1×15 I/Os
DMA
3 Channel
RST/NMI/SBWTDIO
TEST/SBWTCK
PJ.0/TDO
PJ.1/TDI/TCLK
PJ.2/TMS
PJ.3/TCK
EEM
(S: 3+1)
JTAG/
SBW
Interface
MPY32
TA0
TB0
TA1
(2) Timer_A (1) Timer_B
3 CC
3 CC
Registers Registers
RTC_B
CRC
eUSCI_A0:
UART,
IrDA, SPI
eUSCI_B0:
SPI, I2C
REF
Comp_D
12 channels
12
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