MSP430FR573 Datasheet, PDF (42/109 Pages) Texas Instruments – MIXED SIGNAL MICROCONTROLLER

MSP430FR573x
MSP430FR572x
SLAS639D – JULY 2011 – REVISED AUGUST 2012
Table 36. DMA Registers (Base Address DMA General Control: 0500h,
DMA Channel 0: 0510h, DMA Channel 1: 0520h, DMA Channel 2: 0530h)
REGISTER DESCRIPTION
DMA channel 0 control
DMA channel 0 source address low
DMA channel 0 source address high
DMA channel 0 destination address low
DMA channel 0 destination address high
DMA channel 0 transfer size
DMA channel 1 control
DMA channel 1 source address low
DMA channel 1 source address high
DMA channel 1 destination address low
DMA channel 1 destination address high
DMA channel 1 transfer size
DMA channel 2 control
DMA channel 2 source address low
DMA channel 2 source address high
DMA channel 2 destination address low
DMA channel 2 destination address high
DMA channel 2 transfer size
DMA module control 0
DMA module control 1
DMA module control 2
DMA module control 3
DMA module control 4
DMA interrupt vector
REGISTER
DMA0CTL
00h
DMA0SAL
02h
DMA0SAH
04h
DMA0DAL
06h
DMA0DAH
08h
DMA0SZ
0Ah
DMA1CTL
00h
DMA1SAL
02h
DMA1SAH
04h
DMA1DAL
06h
DMA1DAH
08h
DMA1SZ
0Ah
DMA2CTL
00h
DMA2SAL
02h
DMA2SAH
04h
DMA2DAL
06h
DMA2DAH
08h
DMA2SZ
0Ah
DMACTL0
00h
DMACTL1
02h
DMACTL2
04h
DMACTL3
06h
DMACTL4
08h
DMAIV
0Ah
www.ti.com
OFFSET
Table 37. MPU Control Registers (Base Address: 05A0h)
REGISTER DESCRIPTION
MPU control 0
MPU control 1
MPU Segmentation Register
MPU access management
REGISTER
MPUCTL0
MPUCTL1
MPUSEG
MPUSAM
OFFSET
00h
02h
04h
06h
42
Submit Documentation Feedback
Copyright © 2011–2012, Texas Instruments Incorporated