MSP430F23X_14 Datasheet, PDF (62/93 Pages) Texas Instruments – MIXED SIGNAL MICROCONTROLLER

MSP430F23x
MSP430F24x(1)
MSP430F2410
SLAS547I – JUNE 2007 – REVISED DECEMBER 2012
www.ti.com
12-Bit ADC, Built-In Reference
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
V_REF+
Positive built-in
reference voltage
output
TEST CONDITIONS
REF2_5V = 1 for 2.5 V,
I_VREF+max ≤ I_VREF+ ≤ I_VREF+min
REF2_5V = 0 for 1.5 V,
I_VREF+max ≤ I_VREF+ ≤ I_VREF+min
T_A
-40°C to 85°C
105°C
-40°C to 85°C
105°C
V_CC
3V
2.2 V, 3 V
AV_CC(min)
I_VREF+
AV_CC minimum
voltage, positive
built-in reference
active
Load current out of
V_REF+ terminal
REF2_5V = 0,
I_VREF+max ≤ I_VREF+ ≤ I_VREF+min
REF2_5V = 1,
-0.5 mA ≤ I_VREF+ ≤ I_VREF+min
REF2_5V = 1,
-1 mA ≤ I_VREF+ ≤ I_VREF+min
2.2 V
3V
I_L(VREF)+
Load-current
regulation, V_REF+
terminal ⁽¹⁾
I_VREF+ = 500 µA ± 100 µA,
Analog input voltage ≈ 0.75 V,
REF2_5V = 0
I_VREF+ = 500 µA ± 100 µA,
Analog input voltage ≈ 1.25 V,
REF2_5V = 1
2.2 V
3V
3V
Load current
I_VREF+ = 100 µA → 900 µA,
I_{DL(VREF) +} regulation, V_REF+
C_VREF+ = 5 µF, ax ≈ 0.5 × V_REF+,
3V
terminal ⁽²⁾
Error of conversion result ≤ 1 LSB
C_VREF+
T_REF+
Capacitance at pin
V_REF+ ⁽³⁾
Temperature
coefficient of built-in
reference ⁽²⁾
REFON = 1,
0 mA ≤ I_VREF+ ≤ I_VREF+max
I_VREF+ is a constant in the range of
0 mA ≤ I_VREF+ ≤ 1 mA
2.2 V, 3 V
2.2 V, 3 V
t_REFON
Settle time of
internal reference
voltage (see
Figure 39 ) ^{(4) (2)}
I_VREF+ = 0.5 mA, C_VREF+ = 10 µF,
V_REF+ = 1.5 V, V_AVCC = 2.2 V
2.2 V
MIN NOM
2.4 2.5
2.37 2.5
1.44 1.5
1.42 1.5
2.2
MAX
2.6
2.64
1.56
1.57
UNIT
V
2.8
V
2.9
0.01
-0.5
mA
0.01
-1
±2
LSB
±2
±2 LSB
20 ns
5
10
µF
±100 ppm/°C
17 ms
(1) Not production tested, limits characterized.
(2) Not production tested, limits verified by design.
(3) The internal buffer operational amplifier and the accuracy specifications require an external capacitor. All INL and DNL tests uses two
capacitors between pins V_REF+ and AV_SS and V_REF-–/V_eREF– and AV_SS: 10 µF tantalum and 100 nF ceramic.
(4) The condition is that the error in a conversion started after t_REFON is less than ±0.5 LSB. The settling time depends on the external
capacitive load.
C_VREF+
100 µF
10 µF
t_REFON ≈ .66 x C_VREF+ [ms] with C_VREF+ in µF
1 µF
0
1 ms
10 ms
100 ms t_REFON
Figure 39. Typical Settling Time of Internal Reference t_REFON vs External Capacitor on V_REF+
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