MSP430F23X_14 Datasheet, PDF (36/93 Pages) Texas Instruments – MIXED SIGNAL MICROCONTROLLER

MSP430F23x
MSP430F24x(1)
MSP430F2410
SLAS547I – JUNE 2007 – REVISED DECEMBER 2012
www.ti.com
Outputs (Ports P1, P2, P3, P4, P5, P6)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
V_OH
High-level output voltage
V_OL
Low-level output voltage
TEST CONDITIONS
I_OH(max) = -1.5 mA ⁽¹⁾
I_OH(max) = -6 mA ⁽²⁾
I_OH(max) = -1.5 mA⁽¹⁾
I_OH(max) = -6 mA⁽²⁾
I_OL(max) = 1.5 mA⁽¹⁾
I_OL(max) = 6 mA ⁽²⁾
I_OL(max) = 1.5 mA⁽¹⁾
I_OL(max) = 6 mA ⁽²⁾
V_CC
2.2 V
3V
2.2 V
3V
MIN
V_CC - 0.25
V_CC - 0.6
V_CC - 0.25
V_CC - 0.6
V_SS
V_SS
V_SS
V_SS
MAX
V_CC
V_CC
V_CC
V_CC
V_SS + 0.25
V_SS + 0.6
V_SS + 0.25
V_SS + 0.6
UNIT
V
V
(1) The maximum total current, I_OH(max) and I_OL(max), for all outputs combined, should not exceed ±12 mA to hold the maximum voltage drop
specified.
(2) The maximum total current, I_OH(max) and I_OL(max), for all outputs combined, should not exceed ±48 mA to hold the maximum voltage drop
specified.
Output Frequency (Ports P1, P2, P3, P4, P5, P6)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
Port output
f_Px.y
frequency with
load
TEST CONDITIONS
P1.4/SMCLK, C_L = 20 pF, R_L = 1 kΩ⁽¹⁾⁽²⁾
V_CC
2.2 V
3V
MIN TYP
DC
DC
MAX
10
12
UNIT
MHz
f_Port°CLK
Clock output
frequency
P2.0/ACLK/CA2, P1.4/SMCLK, C_L = 20 pF⁽²⁾
2.2 V
3V
DC
DC
12
MHz
16
t_(Xdc)
Duty cycle of
output frequency
P1.0/TACLK/CAOUT, C_L = 20 pF, LF mode
P1.0/TACLK/CAOUT, C_L = 20 pF, XT1 mode
P1.1/TA0, C_L = 20 pF, XT1 mode
P1.1/TA0, C_L = 20 pF, DCO
P1.4/SMCLK, C_L = 20 pF, XT2 mode
P1.4/SMCLK, C_L = 20 pF, DCO
30%
40%
40%
50% – 15 ns
40%
50% – 15 ns
50%
70%
50%
60%
60%
50% 50% + 15 ns
60%
50% + 15 ns
(1) A resistive divider with two 0.5-kΩ resistors between V_CC and V_SS is used as load. The output is connected to the center tap of the
divider.
(2) The output voltage reaches at least 10% and 90% V_CC at the specified toggle frequency.
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