MSP430F23X_14 Datasheet, PDF (19/93 Pages) Texas Instruments – MIXED SIGNAL MICROCONTROLLER

www.ti.com
Memory Organization
Memory
Main: interrupt vector
Main: code memory
RAM (Total)
Information memory
Boot memory
RAM
Peripherals
Size
Flash
Flash
Size
Size
Flash
Size
ROM
Size
16 bit
8 bit
SFR
MSP430F23x
MSP430F24x(1)
MSP430F2410
SLAS547I – JUNE 2007 – REVISED DECEMBER 2012
Table 12. Memory Organization
MSP430F233
8KB
0xFFFF to 0xFFC0
0xFFFF to 0xE000
1KB
0x05FF to 0x0200
256 Byte
0x10FF to 0x1000
1KB
0x0FFF to 0x0C00
1KB
0x05FF to 0x0200
0x01FF to 0x0100
0x00FF to 0x0010
0x000F to 0x0000
MSP430F235
16KB
0xFFFF to 0xFFC0
0xFFFF to 0xC000
2KB
0x09FF to 0x0200
256 Byte
0x10FF to 0x1000
1KB
0x0FFF to 0x0C00
2KB
0x09FF to 0x0200
0x01FF to 0x0100
0x00FF to 0x0010
0x000F to 0x0000
MSP430F249
MSP430F2491
60KB
0xFFFF to 0xFFC0
0xFFFF to 0x1100
2KB
0x09FF to 0x0200
256 Byte
0x10FF to 0x1000
1KB
0x0FFF to 0x0C00
2KB
0x09FF to 0x0200
0x01FF to 0x0100
0x00FF to 0x0010
0x000F to 0x0000
Memory
Main: interrupt vector
Main: code memory
RAM (total)
Extended
Mirrored
Information memory
Boot memory
RAM (mirrored at
0x18FF to 0x1100)
Peripherals
Size
Flash
Flash
Size
Size
Size
Size
Flash
Size
ROM
Size
16 bit
8 bit
SFR
MSP430F247
MSP430F2471
32KB
0xFFFF to 0xFFC0
0xFFFF to 0x8000
4KB
0x20FF to 0x1100
2KB
0x20FF to 0x1900
2KB
0x18FF to 0x1100
256 Byte
0x10FF to 0x1000
1KB
0x0FFF to 0x0C00
2KB
0x09FF to 0x0200
0x01FF to 0x0100
0x00FF to 0x0010
0x000F to 0x0000
MSP430F248
MSP430F2481
48KB
0xFFFF to 0xFFC0
0xFFFF to 0x4000
4KB
0x20FF to 0x1100
2KB
0x20FF to 0x1900
2KB
0x18FF to 0x1100
256 Byte
0x10FF to 0x1000
1KB
0x0FFF to 0x0C00
2KB
0x09FF to 0x0200
0x01FF to 0x0100
0x00FF to 0x0010
0x000F to 0x0000
MSP430F2410
56KB
0xFFFF to 0xFFC0
0xFFFF to 0x2100
4KB
0x20FF to 0x1100
2KB
0x20FF to 0x1900
2KB
0x18FF to 0x1100
256 Byte
0x10FF to 0x1000
1KB
0x0FFF to 0x0C00
2KB
0x09FF to 0x0200
0x01FF to 0x0100
0x00FF to 0x0010
0x000F to 0x0000
Bootstrap Loader (BSL)
The MSP430 bootstrap loader (BSL) enables users to program the flash memory or RAM using a UART serial
interface. Access to the MSP430 memory via the BSL is protected by user-defined password. For complete
description of the features of the BSL and its implementation, see the MSP430 Programming Via the Bootstrap
Loader User’s Guide (SLAU319).
Table 13. BSL Function Pins
BSL FUNCTION
Data transmit
Data receive
PM, RGC PACKAGE PINS
13 - P1.1
22 - P2.2
Flash Memory
The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The
CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:
• Flash memory has n segments of main memory and four segments of information memory (A to D) of
Copyright © 2007–2012, Texas Instruments Incorporated
Submit Documentation Feedback
19