TLK2711-SP_15 Datasheet, PDF (6/29 Pages) Texas Instruments – 1.6-Gbps to 2.5-Gbps Class V Transceiver

TLK2711-SP
SGLS307N – JULY 2006 – REVISED DECEMBER 2015
www.ti.com
PIN
NAME
NO.
LOOPEN
22
PRE
60
PRBSEN
27
RKLSB
30
RKMSB
31
RXCLK
RX_CLK
43
RXD0
54
RXD1
53
RXD2
52
RXD3
49
RXD4
48
RXD5
47
RXD6
46
RXD7
44
RXD8
42
RXD9
41
RXD10
39
RXD11
38
RXD12
37
RXD13
36
RXD14
33
RXD15
32
DINRXN
56
DINRXP
57
TESTEN
28
TKLSB
23
TKMSB
21
TXCLK
GTX_CLK
8
(2) Internal 10-kΩ pulldown
Pin Functions (continued)
I/O
DESCRIPTION
Loop enable. When LOOPEN is active high, the internal loopback path is activated. The transmitted
serial data is directly routed internally to the inputs of the receiver. This provides a self-test
I⁽²⁾ capability in conjunction with the protocol device. The TXP and TXN outputs are held in a high-
impedance state during the loopback test. LOOPEN is held low during standard operational state,
with external serial outputs and inputs active.
Preemphasis control. Selects the amount of preemphasis to be added to the high-speed serial
I⁽²⁾ output drivers. Left low or unconnected, 5% preemphasis is added. Pulled high, 20% preemphasis
is added.
I ⁽²⁾
PRBS test enable. When asserted high, results of pseudo-random bit stream (PRBS) tests can be
monitored on the RKLSB pin. A high on RKLSB indicates that valid PRBS is being received.
K-code indicator/PRBS test results. When RKLSB is asserted high, an 8-bit/10-bit K code was
O
received and is indicated by data bits RXD0 through RXD7. When RKLSB is asserted low, an 8-
bit/10-bit D code is received and is presented on data bits RXD0 through RXD7. When PRBSEN is
asserted high, this pin is used to indicate status of the PRBS test results (high = pass).
K-code indicator. When RKMSB is asserted high an 8-bit/10-bit K code was received and is
indicated by data bits RXD8 through RXD15. When RKMSB is asserted low an 8-bit/10-bit D code
O was received and is presented on data bits RXD8 through RXD15. If the differential signal on RXN
and RXP drops below 200 mV, RXD0–RXD15, RKLSB, and RKMSB are all asserted high. When
device is disabled (ENABLE = L), RKMSB will output the status of LOS. Active low = LOS detected.
Recovered clock. Output clock that is synchronized to RXD0 through RXD9, RKLSB, and RKMSB.
O RXCLK is the recovered serial data rate clock divided by 20. RXCLK is held low during power-on
reset.
Receive data bus. These outputs carry 16-bit parallel data output from the transceiver to the
O protocol device, synchronized to RXCLK. The data is valid on the rising edge of RXCLK as shown
in Figure 10. These pins are in high-impedance state during power-on reset.
I
Serial receive inputs. RXP and RXN together are the differential serial input interface from a copper
or an optical I/F module.
I⁽²⁾ Test mode enable. This pin should be left unconnected or tied low.
K-code generator (LSB). When TKLSB is high, an 8-bit/10-bit K code is transmitted as controlled by
I⁽¹⁾ data bits TXD0 through TXD7. When TKLSB is low, an 8-bit/10-bit D code is transmitted as
controlled by data bits TXD0 through TXD7.
K-code generator (MSB). When TKMSB is high, an 8-bit/10-bit K code is transmitted as controlled
I⁽¹⁾ by data bits TXD8 through TXD15. When TKMSB is low, an 8-bit/10-bit D code is transmitted as
controlled by data bits TXD8 through TXD15.
Reference clock. TXCLK is a continuous external input clock that synchronizes the transmitter
I
interface signals TKMSB, TKLSB, and TXD0–TXD15. The frequency range of TXCLK is 80 to 125
MHz. The transmitter uses the rising edge of this clock to register the 16-bit input data TXD0
through TXD15 for serialization.
6
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