TLK2711-SP_15 Datasheet, PDF (16/29 Pages) Texas Instruments – 1.6-Gbps to 2.5-Gbps Class V Transceiver

TLK2711-SP
SGLS307N – JULY 2006 – REVISED DECEMBER 2015
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8.3.8 Receive Interface
The receiver interface of the TLK2711-SP accepts 8-bit/10-bit encoded differential serial data. The interpolator
and clock recovery circuit locks to the data stream and extracts the bit-rate clock. This recovered clock is used to
retime the input data stream. The serial data is then aligned to two separate 10-bit word boundaries, 8-bit/10-bit
decoded, and output on a 16-bit-wide parallel bus synchronized to the extracted receive clock. The data is
received LSB (RXD0) first.
8.3.9 Receive Data Bus
The receive bus interface drives 16-bit-wide single-ended TTL parallel data at the RXD0 to RXD15 pins. Data is
valid on the rising edge of the RXCLK. The RXCLK is used as the recovered word clock. The data, RKLSB,
RKMSB, and clock signals are aligned as shown in Figure 10. Detailed timing information can be found in the
TTL Output Switching Characteristics.
RXCLK
RXD0−RXD15
t_su
t_h
RKLSB, RKMSB
Figure 10. Receive Timing Waveform
8.3.10 Data Reception Latency
The serial-to-parallel data receive latency is the time from when the first bit arrives at the receiver until it is output
in the aligned parallel word. The receive latency is fixed after the link is established. However, due to silicon
process variations and implementation variables such as supply voltage and temperature, the exact delay varies
slightly. The minimum receive latency t_{d(Rx latency)} is 76 bit times; the maximum is 107 bit times. Figure 11 shows
the timing relationship between the serial receive pins, the recovered word clock (RXCLK), and the receive data
bus.
20-Bit Encoded Word
RXN,
RXP
RXD0−RXD15
t_{d(Rx latency)}
16-Bit Decoded Word
RXCLK
Figure 11. Receiver Latency
8.3.11 Serial to Parallel
Serial data is received on the RXP and RXN pins. The interpolator and clock recovery circuit locks to the data
stream if the clock to be recovered is within 200 PPM of the internally generated bit rate clock. The recovered
clock is used to retime the input data stream. The serial data is then clocked into the serial-to-parallel shift
registers. The 10-bit-wide parallel data is then multiplexed and fed into two separate 8-bit/10-bit decoders, where
the data is then synchronized to the incoming data stream word boundary by detection of the comma 8-bit/10-bit
synchronization pattern.
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