TLK2711-SP_15 Datasheet, PDF (15/29 Pages) Texas Instruments – 1.6-Gbps to 2.5-Gbps Class V Transceiver

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TLK2711-SP
SGLS307N – JULY 2006 – REVISED DECEMBER 2015
Feature Description (continued)
8.3.4 8-Bit/10-Bit Encoder
All true serial interfaces require a method of encoding to ensure minimum transition density, so that the receiving
phase-locked loop (PLL) has a minimal number of transitions to stay locked on. The encoding scheme maintains
the signal DC balance by keeping the number of 1s and 0s the same. This provides good transition density for
clock recovery and improves error checking. The TLK2711-SP uses the 8-bit/10-bit encoding algorithm that is
used by fibre channel and gigabit ethernet. This is transparent to the user, as the TLK2711-SP internally encodes
and decodes the data such that the user reads and writes actual 16-bit data.
The 8-bit/10-bit encoder converts 8-bit-wide data to a 10-bit-wide encoded data character to improve its
transmission characteristics. Because the TLK2711-SP is a 16-bit-wide interface, the data is split into two 8-bit-
wide bytes for encoding. Each byte is fed into a separate encoder. The encoding is dependent upon two
additional input signals, TKMSB and TKLSB.
TKLSB
0
0
1
1
TKMSB
0
1
0
1
Table 1. Transmit Data Controls
16 BIT PARALLEL INPUT
Valid data on TXD0 to TXD7
Valid data TXD8 to TXD15
Valid data on TXD0 to TXD7
K code on TXD8 to TXD15
K code on TXD0 to TXD7
Valid data on TXD8 to TXD15
K code on TXD0 to TXD7
K code on TXD8 to TXD15
8.3.5 Pseudo-Random Bit Stream (PRBS) Generator
The TLK2711-SP has a built-in 2⁷ – 1 PRBS function. When the PRBSEN pin is forced high, the PRBS test is
enabled. A PRBS is generated and fed into the 10-bit parallel-to-serial converter input register. Data from the
normal input source is ignored during the PRBS mode. The PRBS pattern is then fed through the transmit
circuitry as if it were normal data and sent out to the transmitter. The output can be sent to a bit error rate tester
(BERT), the receiver of another TLK2711-SP, or looped back to the receive input. Because the PRBS is not
really random, but a predetermined sequence of 1s and 0s, the data can be captured and checked for errors by
a BERT.
8.3.6 Parallel to Serial
The parallel-to-serial shift register takes in the 20-bit-wide data word multiplexed from the two parallel 8-bit/10-bit
encoders and converts it to a serial stream. The shift register is clocked on both the rising and falling edge of the
internally generated bit clock, which is 10× the TXCLK input frequency. The LSB (TXD0) is transmitted first.
8.3.7 High-Speed Data Output
The high-speed data output driver consists of a voltage mode logic (VML) differential pair optimized for a 50-Ω
impedance environment. The magnitude of the differential-pair signal swing is compatible with pseudo emitter
coupled logic (PECL) levels when AC coupled. The line can be directly coupled or AC coupled. See Figure 13
and Figure 14 for termination details. The outputs also provide preemphasis to compensate for AC loss when
driving a cable or PCB backplane trace over a long distance (see Figure 9). The level of preemphasis is
controlled by PRE (see Table 2).
V_OD(p)
V_OD(d)
0V
Bit
Time
Bit
Time
V_OD(p)
V_OD(d)
Figure 9. Output Voltage Under Preemphasis
(VTXP to VTXN)
Copyright © 2006–2015, Texas Instruments Incorporated
Table 2. Programmable Preemphasis
PRE
0
1
PREEMPHASIS LEVEL (%)
V_OD(P), V_OD(D) ⁽¹⁾
5%
20%
(1) V_OD(p): Voltage swing when there is a transition in the data
stream.
V_OD(d): Voltage swing when there is no transition in the data
stream.
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