TLK2711-SP_15 Datasheet, PDF (14/29 Pages) Texas Instruments – 1.6-Gbps to 2.5-Gbps Class V Transceiver

TLK2711-SP
SGLS307N – JULY 2006 – REVISED DECEMBER 2015
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8.3 Feature Description
8.3.1 Transmit Interface
The transmitter interface registers valid incoming 16-bit-wide data (TXD0 to TXD15) on the rising edge of the
TXCLK. The data is then 8-bit/10-bit encoded, serialized, and transmitted sequentially over the differential high-
speed I/O channel. The clock multiplier multiplies the reference clock (TXCLK) by a factor of 10×, creating a bit
clock. This internal bit clock is fed to the parallel-to-serial shift register, which transmits data on both the rising
and falling edges of the bit clock, providing a serial data rate that is 20× the reference clock. Data is transmitted
least significant bit (LSB) (TXD0) first.
8.3.2 Transmit Data Bus
The transmit data bus interface accepts 16-bit single-ended TTL parallel data at the TXD0–TXD15 pins. Data
and K-code control is valid on the rising edge of the TXCLK. The TXCLK is used as the word clock. The data, K-
code, and clock signals must be properly aligned as shown in Figure 7. Detailed timing information can be found
in the Transmitter/Receiver Electrical Characteristics.
TXCLK
TXD0−TXD15
t_su
t_h
TKLSB, TKMSB
Figure 7. Transmit Timing Waveform
8.3.3 Data Transmission Latency
The data transmission latency of the TLK2711-SP is defined as the delay from the initial 16-bit word load to the
serial transmission of bit 0. The transmit latency is fixed after the link is established. However, due to silicon
process variations and implementation variables such as supply voltage and temperature, the exact delay varies
slightly. The minimum transmit latency t_{d(Tx latency)} is 34 bit times; the maximum is 38 bit times. Figure 8 shows the
timing relationship between the transmit data bus, TXCLK, and serial transmit pins.
TXP,
TXN
TXD0−TXD15
t_{d(Tx latency)}
16-Bit Word to Transmit
Transmitted 20-Bit Word
TXCLK
Figure 8. Transmitter Latency
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