TI380FPAA Datasheet, PDF (6/24 Pages) Texas Instruments – PACKETBLASTERE™

TI380FPAA
PACKETBLASTER ™
SPWS038 – MAY 1997
Terminal Functions (Continued)
TERMINAL
NAME
NO.
I/O†
DESCRIPTION
MRAS
Row-address strobe for DRAMs. The row address lasts for the first 5/16 of the memory cycle. MRAS
23
O
is driven low every memory cycle while the row address is valid on MADL0 – MADL7, MAXPH, and
MAXPL for both RAM and register-access cycles.
MRESET
Memory-bus reset. MRESET is the reset signal provided by the TI380C2x or TI380C3x and is used to
41
I
reset and initialize the FPA internal logic. While MRESET is asserted, all FPA output pins are in the
high-impedance state.
Local-memory write. MW is used to specify a write cycle on the local-memory bus. The data on the
MADH0 – MADH7 and MADL0 – MADL7 buses is valid while MW is low. DRAMs latch data on the falling
MW
24
O
edge MW, while SRAMs latch data on the rising edge of MW.
H = Not a local-memory write cycle
L = Local-memory write cycle
NC
33
42
No connect. Do not connect these pins.
PLLCAP
45
I
Phase-locked loop (PLL) tuning capacitor (see Note 3)
VDDL
17
36
I
Positive supply voltage for digital logic. All VDDL pins must be attached to the common system power
supply plane.
VDD
3
16
29
I
Positive supply voltage for output buffers. All VDD pins must be attached to the common system power
supply plane.
PLLVDD
VSSC
46
I
Positive supply voltage for phase-locked loop (see Note 4)
1
14
27
I
Ground reference for output buffers (clean ground). All VSSC pins must be attached to the common
system ground plane.
VSSL
11
40
I
Ground reference for digital logic. All VSSL pins must be attached to the common system ground plane.
VSS
12
25
I
Ground connections for output buffers. All VSS pins must be attached to common system ground plane.
51
PLLVSS
44
I
Ground reference for phase-locked loop. Attach to the common system ground plane.
† _{I = input, O = output}
NOTES: 3. The PLLCAP requires the following connection:
These components must be placed as close as
possible to PLLCAP.
PLLCAP
3.3 kΩ
GND
4. Isolate PLLVDD to a separate PLL power pad with
ferrite bead separation from the common system
power supply plane. A 0.1-µF decoupling capacitor
on PLLVDD is also necessary as shown. These
components must be placed as close as possible to
PLLVDD.
PLLVDD
GND
0.1 µF
GND
1000 pF
VDD
0.1 µF
6
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