TI380FPAA Datasheet, PDF (18/24 Pages) Texas Instruments – PACKETBLASTERE™

TI380FPAA
PACKETBLASTER ™
SPWS038 – MAY 1997
tiiming requirements over recommended operating conditions for FPA slave: read cycle (see
Figure 10)
t_M is the cycle time of one-eighth of a local-memory cycle (20.83 ns minimum for a 6-MHz local bus or
31.25 ns minimum for a 4-MHz local bus).
NO.
84 Setup time, address on MAX0, MAX2 before MBCLK1 falling edge, FPA-slave read
85 Hold time, address on MAX0, MAX2 after MBCLK1 falling edge, FPA-slave read
86 Setup time, valid address before MBCLK1 falling edge, FPA-slave read
87 Hold time, valid address after MBCLK1 falling edge, FPA-slave read
Setup time, address in the high-impedance state before MBCLK1 falling edge,
88 _{FPA-slave read}
89 Setup time, data/parity valid after MBCLK1 falling edge, FPA-slave read
90 Hold time, data/parity valid after MBCLK1 falling edge, FPA-slave read
91
Setup time, data/parity in the high-impedance state after MBCLK1 falling edge,
FPA-slave read
92 Setup time, MDDIR low after MBCLK1 falling edge, FPA-slave read
93 Hold time, MDDIR low after MBCLK1 falling edge, FPA-slave read
MIN
10
0
10
0
0
0.5tM + 10
2tM
2tM + 9
tM – 15
tM
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
M8 M1 M2 M3 M4 M5 M6 M7 M8 M1
tM
MBCLK1
84
85
MAX0, MAX2
Address
MAXPH, MAXPL,
MADL0 – MADL7,
MADH0 – MADH7
MDDIR
86
87
Address
93
92
88
90
91
89
Data
Out
Figure 10. FPA Slave Timing: Read Cycle
18
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