TI380FPAA Datasheet, PDF (21/24 Pages) Texas Instruments – PACKETBLASTERE™

TI380FPAA
PACKETBLASTER ™
SPWS038 – MAY 1997
FPA bus arbitration: FPA takes control of bus (see Figure 14)
t_M is the cycle time of one-eighth of a local-memory cycle (20.83 ns minimum for a 6-MHz local bus or
31.25 ns minimum for a 4-MHz local bus).
NO.
79 Hold time, FPA valid in the high-impedance state after MBCLK1 falling edge, bus-resume
80 Delay time, MBCLK1 falling edge to FPA valid, bus-resume
MIN
2tM – 13
MAX
2tM + 9
UNIT
ns
ns
MBCLK1
79
MAX0,
MAX2
MAXPH,
MAXPL,
MADH0 – MADH7,
MADL0 – MADL7
MRAS
MCAS
MW
MOE
MBEN
MDDIR
MAL
80
Figure 14. FPA Bus Arbitration: FPA Takes Control of Bus
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