TI380FPAA Datasheet, PDF (13/24 Pages) Texas Instruments – PACKETBLASTERE™

TI380FPAA
PACKETBLASTER ™
SPWS038 – MAY 1997
FPA bus master timing: MRAS, MCAS, and MAL to ADDRESS (see Figure 7)
t_M is the cycle time of one-eighth of a local-memory cycle (20.83 ns minimum for a 6-MHz local bus or
31.25 ns minimum for a 4-MHz local bus).
NO.
MIN
MAX UNIT
15
Setup time, row address on MADL0 – MADL7, MAXPH, and MAXPL before MRAS no longer high 1.5tM – 11.5
ns
16
Hold time, row address on MADL0 – MADL7, MAXPH, and MAXPL after MRAS no longer high
tM – 6.5
ns
17
Delay time, MRAS no longer high to MRAS no longer high in the next memory cycle
8tM
ns
18
Pulse duration, MRAS low
4.5tM – 9
ns
19
Pulse duration, MRAS high
3.5tM – 9
ns
20
Setup time, column address (MADL0 – MADL7, MAXPH, and MAXPL) and status
(MADH0 – MADH7) before MCAS no longer high
0.5tM – 9
ns
21
Hold time, column address (MADL0 – MADL7, MAXPH, and MAXPL) and status
(MADH0 – MADH7) after MCAS low
tM – 9
ns
Hold time, column address (MADL0 – MADL7, MAXPH, and MAXPL) and status
22
(MADH0 – MADH7) after MRAS no longer high
2.5tM – 6.5
ns
23
Pulse duration, MCAS low
3tM – 9
ns
24
Pulse duration, MCAS high, refresh cycle follows read or write cycle
2tM – 9
ns
25
Hold time, row address on MADL0 – MADL7, MAXPH, and MAXPL after MAL low
1.5tM – 9
ns
26
Setup time, row address on MADL0 – MADL7, MAXPH, and MAXPL before MAL no longer high
tM – 9
ns
27
Pulse duration, MAL high
tM – 9
ns
28
Setup time, address/enable on MAX0 and MAX2 before MAL no longer high
tM – 9
ns
29
Hold time, address/enable of MAX0 and MAX2 after MAL low
1.5tM – 9
ns
30
Setup time, address on MADH0 – MADH7 before MAL no longer high
tM – 9
ns
31
Hold time, address on MADH0 – MADH7 after MAL low
1.5tM – 9
ns
• POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443
13