TI380FPAA Datasheet, PDF (19/24 Pages) Texas Instruments – PACKETBLASTERE™

TI380FPAA
PACKETBLASTER ™
SPWS038 – MAY 1997
timing requirements over recommended operating conditions for FPA slave: write cycle (see
Figure 11)
t_M is the cycle time of one-eighth of a local-memory cycle (20.83 ns minimum for a 6-MHz local bus or
31.25 ns minimum for a 4-MHz local bus).
NO.
84 Setup time, address on MAX0, MAX2 before MBCLK1 falling edge, FPA-slave read
85 Hold time, address on MAX0, MAX2 after MBCLK1 falling edge, FPA-slave read
86 Setup time, valid address before MBCLK1 falling edge, FPA-slave read
87 Hold time, valid address after MBCLK1 falling edge, FPA-slave read
96 Setup time, valid data/parity after MBCLK1 falling edge, FPA-slave write
97 Hold time, valid data/parity after MBCLK1 falling edge, FPA-slave write
98 Setup time, MDDIR high after MBCLK1 falling edge, FPA-slave write
99 Hold time, MDDIR high after MBCLK1 falling edge, FPA-slave read
MIN
10
0
10
0
tM – 15
tM
tM – 15
tM
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
M8 M1 M2 M3 M4 M5 M6 M7 M8 M1
tM
MBCLK1
84
85
MAX0, MAX2
Address
MAXPH, MAXPL,
MADL0 – MADL7,
MADH0 – MADH7
86
87
Address
99
98
97
96
Data
In
MDDIR
Figure 11. FPA Slave Timing: Write Cycle
• POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443
19