TI380FPAA Datasheet, PDF (11/24 Pages) Texas Instruments – PACKETBLASTERE™

TI380FPAA
PACKETBLASTER ™
SPWS038 – MAY 1997
timing requirements over recommended operating conditions for power up, MBCLK1, and
MRESET (see Figure 4)
NO.
100† tr(VDD)
Rise time, 1.2 V to minimum VDD-high level
111† td(CKV)
Delay time, minimum VDD-high level to MBCLK1 valid
117† th(VDDH-RSL) Hold time, MRESET low after VDD reaches minimum high level
118† tw(RSH)
Pulse duration, MRESET high
119† tw(RSL)
Pulse duration, MRESET low
† _{This specification is provided as an aid to board design. It is not assured during manufacturing testing.}
MIN MAX UNIT
1 ms
3 ms
5
ms
14
µs
14
µs
100
VDD
Minimun VDD High Level
MBCLK1
MRESET
111
117
118
119
NOTE A: In order to represent the information in one illustration, nonactual phase and timebase characteristics are shown. Refer to specified
parameters for precise information.
Figure 4. Power Up, MBCLK1, and MRESET Timing
timing requirements over recommended operating conditions for MBCLK1 (see Figure 5)
t_M is the cycle time of one-eighth of a local-memory cycle (20.83 ns minimum for a 6-MHz local bus or
31.25 ns minimum for a 4-MHz local bus).
NO.
1 Period of MBCLK1
2 Pulse duration, MBCLK1 high
3 Pulse duration, MBCLK1 low
4 Transition time, MBCLK1
MIN
4tM
2tM – 9
2tM – 9
5
MAX
UNIT
ns
ns
ns
ns
tM
MBCLK1
M8 M1 M2 M3 M4 M5 M6 M7 M8 M1
1
3
2
4
4
Figure 5. Clock Timing: MBCLK1
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