TI380FPAA Datasheet, PDF (12/24 Pages) Texas Instruments – PACKETBLASTERE™

TI380FPAA
PACKETBLASTER ™
SPWS038 – MAY 1997
timing requirements over recommended operating conditions for FPA bus master: MAL, MRESET,
and address (see Figure 6)
t_M is the cycle time of one-eighth of a local-memory cycle (20.83 ns minimum for a 6-MHz local bus or
31.25 ns minimum for a 4-MHz local bus).
NO.
MIN
MAX UNIT
8 Setup time, address/enable on MAX0 and MAX2 before MBCLK1 no longer high
tM – 9
ns
9 Setup time, row address on MADL0 – MADL7, MAXPH, and MAXPL before MBCLK1 no longer high tM – 14
ns
10 Setup time, address on MADH0 – MADH7 before MBCLK1 no longer high
tM – 14
ns
11 Setup time, MAL high before MBCLK1 no longer high
tM – 13
ns
12 Setup time, address on MAX0 and MAX2 before MBCLK1 no longer low
0.5tM – 9
ns
13
Setup time, column address on MADL0 – MADL7, MAXPH, and MAXPL before MBCLK1 no
longer low
0.5tM – 9
ns
14 Setup time, status on MADH0 – MADH7 before MBCLK1 no longer low
126 Delay time, MBCLK1 no longer low to MRESET valid
0.5tM – 9
0
ns
20 ns
129 Hold time, column address/status after MBCLK1 no longer low
tM – 7
ns
M8 M1 M2 M3 M4 M5 M6 M7 M8 M1
tM
MBCLK1
MAX0,
MAX2
MAXPH,
MAXPL,
MADL0 – MADL7
MADH0 – MADH7
MAL
8
12
ADD/EN
Address
9
Row
13
Col
10
14
Address
Status
11
129
MRESET
126
Valid
Figure 6. FPA Bus Master Timing: MAL, MRESET, and ADDRESS
12
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