DS90UB901Q_15 Datasheet, PDF (6/50 Pages) Texas Instruments – 10 - 43MHz 14 Bit Color FPD-Link III Serializer and Deserializer with Bidirectional Control Channel

DS90UB901Q, DS90UB902Q
SNLS322E – JUNE 2010 – REVISED APRIL 2013
www.ti.com
DS90UB902Q DESERIALIZER PIN DESCRIPTIONS (continued)
Pin Name
MODE
Pin No.
40
I/O, Type
Input, LVCMOS
w/ pull up
Description
I²C Mode select
MODE = L, Master mode; Device generates and drives the SCL clock line, where
required such as Read. Device is connected to slave peripheral on the bus.
MODE = H, Slave mode (default); Device accepts SCL clock input and attached to an
I²C controller master on the bus. Slave mode does not generate the SCL clock, but
uses the clock generated by the Master for the data transfers.
ID[x]
1
Input, analog
Device ID Address Select
Resistor to Ground and 10 kΩ pull-up to 1.8V rail. See Table 4
CONTROL AND CONFIGURATION
PDB
Power down Mode Input Pin.
29
Input, LVCMOS
w/ pull down
PDB = H, Deserializer is enabled and is ON.
PDB = L, Deserializer is in Power Down mode. When the Deserializer is in Power
Down. Programmed control register data are NOT retained and reset to default
values.
LOCK
LOCK Status Output Pin.
28
Output,
LVCMOS
LOCK = H, CDR/PLL is Locked, outputs are active
LOCK = L, CDR/PLL is unlocked, the LVCMOS Outputs depend on OSS_SEL control
register, the CDR/PLL is shutdown and IDD is minimized. May be used as Link
Status.
PASS
31
Output,
LVCOMS
When BISTEN = L; Normal operation
PASS is high to indicate no errors are detected. The PASS pin asserts low to indicate
a CRC error was detected on the Link.
RES
32, 33, 39
Reserved
-
Pin 39: This pin MUST be tied LOW.
Pins 32,33: Route to test point or leave open if unused. See also FPD-LINK III
INTERFACE pin description section.
BIST MODE
BISTEN
37
Input, LVCMOS
w/ pull down
BIST Enable Pin.
BISTEN = H, BIST Mode is enabled.
BISTEN = L, BIST Mode is disabled.
PASS
PASS Output Pin for BIST mode.
31
Output,
LVCOMS
PASS = H, ERROR FREE Transmission
PASS = L, one or more errors were detected in the received payload.
Leave Open if unused. Route to test point (pad) recommended.
FPD-LINK III INTERFACE
RIN+
35
Input/Output, Non-inverting differential input, bidirectional control channel output. The interconnect
CML
must be AC Coupled with a 100 nF capacitor.
RIN-
36
Input/Output, Inverting differential input, bidirectional control channel output. The interconnect must
CML
be AC Coupled with a 100 nF capacitor.
CMLOUTP
Non-inverting CML Output
32
Output, CML Monitor point for equalized differential signal. Test port is enabled via control
registers.
CMLOUTN
Inverting CML Output
33
Output, CML Monitor point for equalized differential signal. Test port is enabled via control
registers.
POWER AND GROUND
VDDSSCG
4
Power, Digital
SSCG Power, 1.8V ±5%
Power supply must be connected regardless if SSCG function is in operation.
VDDIO1/2/3
VDDD
25, 16, 8
13
Power, Digital
Power, Digital
LVTTL I/O Buffer Power, The single-ended outputs and control input are powered
from V_DDIO. V_DDIO can be connected to a 1.8V ±5% or 3.3V ±10%
Digital Core Power, 1.8V ±5%
VDDR
30
Power, Analog Rx Analog Power, 1.8V ±5%
VDDCML
34
Power, Analog Bidirectional Channel Driver Power, 1.8V ±5%
VDDPLL
38
Power, Analog PLL Power, 1.8V ±5%
VSS
DAP
Ground, DAP
DAP must be grounded. DAP is the large metal contact at the bottom side, located at
the center of the WQFN package. Connected to the ground plane (GND) with at least
16 vias.
6
Submit Documentation Feedback
Copyright © 2010–2013, Texas Instruments Incorporated
Product Folder Links: DS90UB901Q DS90UB902Q