DS90UB901Q_15 Datasheet, PDF (10/50 Pages) Texas Instruments – 10 - 43MHz 14 Bit Color FPD-Link III Serializer and Deserializer with Bidirectional Control Channel

DS90UB901Q, DS90UB902Q
SNLS322E – JUNE 2010 – REVISED APRIL 2013
Recommended Serializer Timing for PCLK⁽¹⁾
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
t_TCP
t_TCIH
t_TCIL
Transmit Clock Period
Transmit Clock Input High
Time
Transmit Clock Input Low
Time
10 MHz – 43 MHz
23.3
0.4T
0.4T
T
0.5T
0.5T
t_CLKT
PCLK Input Transition Time
(Figure 11)
0.5
f_OSC
Internal oscillator clock
source
25
(1) Recommended Input Timing Requirements are input specifications and not tested in production.
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Max
100
0.6T
0.6T
3
Units
ns
ns
ns
ns
MHz
Serializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
t_LHT
CML Low-to-High Transition
Time
R_L = 100Ω (Figure 6)
150
t_HLT
CML High-to-Low Transition
Time
R_L = 100Ω (Figure 6)
150
t_DIS
Data Input Setup to PCLK
2.0
Serializer Data Inputs (Figure 12)
t_DIH
Data Input Hold from PCLK
2.0
t_PLD
Serializer PLL Lock Time
R_L = 100Ω^{(1) (2)}
1
t_SD
Serializer Delay
R_T = 100Ω, PCLK = 10–43 MHz
Register 0x03h b[0] (TRFB = 1)
(Figure 14)
6.386T + 5 6.386T + 12
t_JIND
Serializer output
Serializer Output Deterministic
Jitter
intrinsic deterministic jitter .
Measured (cycle-cycle) with
PRBS-7 test pattern
0.13
PCLK = 43 MHz⁽³⁾⁽⁴⁾
t_JINR
Serializer output intrinsic random
Serializer Output Random
Jitter
jitter (cycle-cycle). Alternating-1,0
pattern.
0.04
PCLK = 43 MHz⁽³⁾⁽⁴⁾
t_JINT
Serializer output peak-to-peak jitter
includes deterministic jitter,
Peak-to-peak Serializer Output
Jitter
random jitter, and jitter transfer
from serializer input. Measured
(cycle-cycle) with PRBS-7 test
pattern.
PCLK = 43 MHz⁽³⁾⁽⁴⁾
0.396
λ_STXBW
Serializer Jitter Transfer
Function -3 dB Bandwidth
PCLK = 43 MHz, Default Registers
(Figure 20)⁽³⁾
1.90
δ_STX
Serializer Jitter Transfer
Function (Peaking)
PCLK = 43 MHz, Default Registers
(Figure 20)⁽³⁾
0.944
δ_STXf
Serializer Jitter Transfer
PCLK = 43 MHz, Default Registers
Function (Peaking Frequency) (Figure 20)⁽³⁾
500
Max
330
330
2
6.386T +
19.7
Units
ps
ps
ns
ns
ms
ns
UI
UI
UI
MHz
dB
kHz
(1) t_PLD and t_DDLT is the time required by the serializer and deserializer to obtain lock when exiting power-down state with an active PCLK
(2) Specification is by design.
(3) Typical values represent most likely parametric norms at 1.8V or 3.3V, T_A = +25°C, and at the Recommended Operation Conditions at
the time of product characterization and are not ensured.
(4) UI – Unit Interval is equivalent to one ideal serialized data bit width. The UI scales with PCLK frequency.
10
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