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DS90UB901Q_15 Datasheet, PDF (37/50 Pages) Texas Instruments – 10 - 43MHz 14 Bit Color FPD-Link III Serializer and Deserializer with Bidirectional Control Channel
DS90UB901Q, DS90UB902Q
www.ti.com
APPLICATIONS INFORMATION
SNLS322E – JUNE 2010 – REVISED APRIL 2013
AC COUPLING
The SER/DES supports only AC-coupled interconnects through an integrated DC balanced decoding scheme.
External AC coupling capacitors must be placed in series in the FPD-Link III signal path as illustrated in
Figure 38.
DOUT+
D
DOUT-
RIN+
R
RIN-
Figure 38. AC-Coupled Connection
For high-speed FPD-Link III transmissions, the smallest available package should be used for the AC coupling
capacitor. This will help minimize degradation of signal quality due to package parasitics. The I/O’s require a 100
nF AC coupling capacitors to the line.
TYPICAL APPLICATION CONNECTION
Figure 39 shows a typical connection of the DS90UB901Q Serializer.
VDDIO
C12 C8
FB1
C3
DS90UB901Q (SER)
VDDIO
VDDT
C4
FB2
1.8V
C9 C13
LVCMOS
Parallel
Bus
DIN0
DIN1
DIN2
DIN3
DIN4
DIN5
DIN6
DIN7
DIN8
DIN9
DIN10
DIN11
DIN12
DIN13
HSYNC
VSYNC
PCLK
I2C
Bus
Interface
LVCMOS
Control
Interface
GPIO
Control
Interface
FB6
FB7
Optional
MODE
PDB
GPIO[0]
GPIO[1]
VDDIO
RPU
C14
RPU
SCL
SDA
C15
Optional
VDDPLL
C10 C5
FB3
VDDCML
C11 C6
FB4
VDDD
C7
FB5
C1
DOUT+
DOUT-
C2
Serial
FPD-Link III
Interface
ID[X]
RES
DAP (GND)
1.8V
10 k:
RID
NOTE:
C1 - C2 = 0.1 PF (50 WV)
C3 - C9 = 0.1 PF
C10 - C13 = 4.7 PF
C14 - C15 = >100 pF
RPU = 1 k: to 4.7 k:
RID (see ID[x] Resistor Value Table)
FB1 - FB7: Impedance = 1 k: (@ 100 MHz)
low DC resistance (<1:)
The "Optional" components shown are
provisions to provide higher system noise
immunity and will therefore result in higher
performance.
Figure 39. DS90UB901Q Typical Connection Diagram — Pin Control
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