DS90UB901Q_15 Datasheet, PDF (26/50 Pages) Texas Instruments – 10 - 43MHz 14 Bit Color FPD-Link III Serializer and Deserializer with Bidirectional Control Channel

DS90UB901Q, DS90UB902Q
SNLS322E – JUNE 2010 – REVISED APRIL 2013
www.ti.com
Bus Activity:
Master
SDA Line S
Slave
Address
7-bit Address 0
Register
Address
Data
P
Bus Activity:
Slave
A
A
A
C
C
C
K
K
K
Figure 24. Write Byte
Bus Activity:
Master
Slave
Address
Register
Address
Slave
Address
SDA Line S
7-bit Address 0
S
7-bit Address 1
Bus Activity:
Slave
A
A
A
C
C
C
K
K
K
Figure 25. Read Byte
Data
N
A
C
K
P
SDA
SCL
START
MSB
1
7-bit Slave Address
2
6
LSB
ACK
R/W
Direction
Bit
Acknowledge
from the Device
MSB
7
8
9
1
Data Byte
2
LSB N/ACK
*Acknowledge
or Not-ACK
8
9
Repeated for the Lower Data Byte
and Additional Data Transfers
STOP
Figure 26. Basic Operation
SDA
SCL
S
START condition, or
START repeat condition
P
STOP condition
Figure 27. START and STOP Conditions
SLAVE CLOCK STRETCHING
In order to communicate and synchronize with remote devices on the I2C bus through the bidirectional control
channel, slave clock stretching must be supported by the I2C master controller/MCU. The chipset utilizes bus
clock stretching (holding the SCL line low) during data transmission; where the I2C slave pulls the SCL line low
prior to the 9th clock of every I2C data transfer (before the ACK signal). The slave device will not control the
clock and only stretches it until the remote peripheral has responded.
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