DS90UB901Q_15 Datasheet, PDF (11/50 Pages) Texas Instruments – 10 - 43MHz 14 Bit Color FPD-Link III Serializer and Deserializer with Bidirectional Control Channel

DS90UB901Q, DS90UB902Q
www.ti.com
SNLS322E – JUNE 2010 – REVISED APRIL 2013
Deserializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Pin/Freq.
Min
t_RCP
Receiver Output Clock Period
t_RCP = t_TCP
t_PDC
PCLK Duty Cycle
Default Registers
SSCG[3:0] = OFF
PCLK
PCLK
23.3
45
t_CLH
LVCMOS Low-to-High Transition V_DDIO: 1.71V to 1.89V or
Time
3.0V to 3.6V,
1.3
t_CHL
LVCMOS High-to-Low Transition
C_L = 8 pF (lumped load) PCLK
Default Registers
Time
(Figure 16)⁽¹⁾
1.3
t_CLH
t_CHL
LVCMOS Low-to-High Transition
Time
LVCMOS High-to-Low Transition
V_DDIO: 1.71V to 1.89V or
3.0V to 3.6V,
C_L = 8 pF (lumped load)
Default Registers
ROUT[13:0],
HSYNC, VSYNC
Time
(Figure 16)⁽¹⁾
1.6
1.6
t_ROS
t_ROH
ROUT Setup Data to PCLK
ROUT Hold Data to PCLK
V_DDIO: 1.71V to 1.89V or
3.0V to 3.6V,
C_L = 8 pF (lumped load)
Default Registers
(Figure 18)
ROUT[13:0],
HSYNC, VSYNC
0.38T
0.38T
t_DD
t_DDLT
t_RJIT
Deserializer Delay
Deserializer Data Lock Time
Receiver Input Jitter Tolerance
Default Registers
Register 0x03h b[0]
(RRFB = 1) (Figure 17)
(Figure 15)⁽²⁾
(Figure 19,
Figure 21)⁽³⁾⁽⁴⁾
10 MHz–43 MHz
10 MHz–43 MHz
43 MHz
4.571T
+8
t_RCJ
Receiver Clock Jitter
PCLK
SSCG[3:0] = OFF⁽¹⁾⁽⁵⁾
10 MHz
43 MHz
t_DPJ
Deserializer Period Jitter
PCLK
SSCG[3:0] = OFF⁽¹⁾⁽⁶⁾
10 MHz
43 MHz
t_DCCJ
Deserializer Cycle-to-Cycle Clock PCLK
Jitter
SSCG[3:0] = OFF⁽⁷⁾⁽¹⁾
10 MHz
43 MHz
fdev
fmod
Spread Spectrum Clocking
Deviation Frequency
Spread Spectrum Clocking
Modulation Frequency
LVCMOS Output Bus
SSC[3:0] = ON
(Figure 22)
20 MHz–43 MHz
20 MHz–43 MHz
Typ
Max
T
100
50
55
2.0
2.8
2.0
2.8
2.4
3.3
2.4
3.3
0.5T
0.5T
4.571T 4.571T
+ 12
+ 16
10
0.53
300
550
120
250
425
600
320
480
320
500
300
500
±0.5% to
±2.0%
9 kHz to
66 kHz
Units
ns
%
ns
ns
ns
ns
ms
UI
ps
ps
ps
%
kHz
(1) Specification is by characterization and is not tested in production.
(2) t_PLD and t_DDLT is the time required by the serializer and deserializer to obtain lock when exiting power-down state with an active PCLK
(3) UI – Unit Interval is equivalent to one ideal serialized data bit width. The UI scales with PCLK frequency.
(4) t_RJIT max (0.61UI) is limited by instrumentation and actual t_RJIT of in-band jitter at low frequency (<2 MHz) is greater 1 UI.
(5) t_DCJ is the maximum amount of jitter measured over 30,000 samples based on Time Interval Error (TIE).
(6) t_DPJ is the maximum amount the period is allowed to deviate measured over 30,000 samples.
(7) t_DCCJ is the maximum amount of jitter between adjacent clock cycles measured over 30,000 samples.
Copyright © 2010–2013, Texas Instruments Incorporated
Submit Documentation Feedback
11
Product Folder Links: DS90UB901Q DS90UB902Q