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| DS90UB901Q_15 Datasheet, PDF (38/50 Pages) Texas Instruments – 10 - 43MHz 14 Bit Color FPD-Link III Serializer and Deserializer with Bidirectional Control Channel | |||
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DS90UB901Q, DS90UB902Q
SNLS322E â JUNE 2010 â REVISED APRIL 2013
Figure 40 shows a typical connection of the DS90UB902Q Deserializer.
1.8V
C13 C11
FB1
FB2
FB3
DS90UB902Q (DES)
VDDIO
VDDD
C3
VDDIO1
C8
FB6 C12 C14
VDDR
C4
VDDIO2
C9
VDDSSCG
VDDIO3
C5
C10
FB4
C15 C6
Serial
FPD-Link III
Interface
FB5
C16 C7
C1
C2
LVCMOS
Control
Interface
TP_A
TP_B
VDDPLL
VDDCML
RIN+
RIN-
RES_PIN32
RES_PIN33
MODE
PDB
ROUT0
ROUT1
ROUT2
ROUT3
ROUT4
ROUT5
ROUT6
ROUT7
ROUT8
ROUT9
ROUT10
ROUT11
ROUT12
ROUT13
HSYNC
VSYNC
PCLK
LVCMOS
Parallel
Bus
VDDIO
RPU
RPU
I2C
Bus
Interface
SCL
FB7
SDA
FB8
C17
C18
Optional
NOTE:
Optional
C1 - C2 = 0.1 PF (50 WV)
C3 - C12 = 0.1 PF
C13 - C16 = 4.7 PF
C17 - C18 = >100 pF
RPU = 1 k: to 4.7 k:
RID (see ID[x] Resistor Value Table)
FB1 - FB8: Impedance = 1 k: (@ 100 MHz)
low DC resistance (<1:)
RES_PIN39
DAP (GND)
The "Optional" components shown are
provisions to provide higher system noise
immunity and will therefore result in higher
performance.
GPIO[0]
GPIO[1]
LOCK
PASS
ID[X]
GPIO
Control
Interface
1.8V
10 k:
RID
Figure 40. DS90UB902Q Typical Connection Diagram â Pin Control
www.ti.com
TRANSMISSION MEDIA
The Ser/Des chipset is intended to be used over a wide variety of balanced cables depending on distance and
signal quality requirements. The Ser/Des employ internal termination providing a clean signaling environment.
The interconnect for FPD-Link III interface should present a differential impedance of 100 Ohms. Use of cables
and connectors that have matched differential impedance will minimize impedance discontinuities. Shielded or
un-shielded cables may be used depending upon the noise environment and application requirements. The
chipset's optimum cable drive performance is achieved at 43 MHz at 10 meters length. The maximum signaling
38
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Copyright © 2010â2013, Texas Instruments Incorporated
Product Folder Links: DS90UB901Q DS90UB902Q
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