DS90UB901Q_15 Datasheet, PDF (18/50 Pages) Texas Instruments – 10 - 43MHz 14 Bit Color FPD-Link III Serializer and Deserializer with Bidirectional Control Channel

DS90UB901Q, DS90UB902Q
SNLS322E – JUNE 2010 – REVISED APRIL 2013
www.ti.com
Table 1. DS90UB901Q Control Registers
Addr
(Hex)
Name
Bits Field
R/W Default Description
7:1 DEVICE ID
0
I²C Device ID
0 SER ID SEL
7-bit address of Serializer; 0x58'h
(1011_000X'b) default
RW
0xB0'h
0: Device ID is from ID[x]
1: Register I²C Device ID overrides ID[x]
7:3 RESERVED
0x00'h Reserved
2 STANDBY
1
Reset
Standby mode control. Retains control register data.
Supported only when MODE = 0
RW
0
0: Enabled. Low-current Standby mode with wake-up
capability. Suspends all clocks and functions.
1: Disabled. Standby and wake-up disabled
1
DIGITAL
RESET0
RW
0
1: Resets the device to default register values. Does not
self clear affect device I²C Bus or Device ID
0 DIGITAL RESET1
RW
0
1: Digital Reset, retains all register values
self clear
2
Reserved
7:0 RESERVED
0x20'h Reserved
CRC Fault
Tolerant
Transmission
RX CRC
7 CHECKER
ENABLE
6
TX CRC GEN
ENABLE
Back Channel CRC Enable
0: Disable
RW
1
1: Enable
For proper CRC operation, on Deserailizer 0x03h b[6]
control register must be Enabled.
Foward Channel CRC Enable
0: Disable
RW
1
1: Enable
For proper CRC operation, on Deserailizer 0x03h b[7]
control register must be Enabled.
VDDIO Control
5 VDDIO CONTOL
RW
Auto V_DDIO detect
1
Allows manual setting of VDDIO by register.
0: Disable
1: Enable (auto detect mode)
VDDIO voltage set
3
VDDIO Mode
4 VDDIO MODE
RW
1
Only used when VDDIOCONTROL = 0
0: 1.8V
1: 3.3V
I²C Pass-Through
3
I²C PASS-
THROUGH
I²C Pass-Through
RW
1
0: Disabled
1: Enabled
RESERVED
2 RESERVED
0
Reserved
PCLK_AUTO
1 PCLK_AUTO
Switch over to internal 25 MHz Oscillator clock in the
RW
1
absence of PCLK
0: Disable
1: Enable
TRFB
0 TRFB
Pixel Clock Edge Select:
0: Parallel Interface Data is strobed on the Falling Clock
RW
1
Edge.
1: Parallel Interface Data is strobed on the Rising Clock
Edge.
7:6 RESERVED
10'b Reserved
4
CRC
Transmission
5 CRC RESET
RW
0
1: CRC Reset.
Clears CRC Error counter.
4:0 RESERVED
5
I²C Bus Rate
7:0 I²C BUS RATE
00000'b Reserved
I²C SCL frequency is determined by the following:
RW
0x40'h
f_SCL = 6.25 MHz / Register value (in decimal)
0x40'h = ~100 kHz SCL (default)
Note: Register values <0x32'h are NOT supported.
6
DES ID
7:1 DES DEV ID
RW
0xC0'h Deserializer Device ID = 0x60'h
(1100_000X'b) default
0 RESERVED
Reserved
18
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