DS90UB901Q_15 Datasheet, PDF (4/50 Pages) Texas Instruments – 10 - 43MHz 14 Bit Color FPD-Link III Serializer and Deserializer with Bidirectional Control Channel

DS90UB901Q, DS90UB902Q
SNLS322E – JUNE 2010 – REVISED APRIL 2013
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DS90UB901Q SERIALIZER PIN DESCRIPTIONS (continued)
Pin Name
Pin No.
I/O, Type
Description
SDA
MODE
5
Input/Output, Data line for the bidirectional control bus communication
Open Drain SDA requires an external pull-up resistor to V_DDIO.
I²C Mode select
MODE = L, Master mode (default); Device generates and drives the SCL clock line.
8
Input, LVCMOS
w/ pull down
Device is connected to slave peripheral on the bus. (Serializer initially starts up in
Standby mode and is enabled through remote wakeup by Deserializer)
MODE = H, Slave mode; Device accepts SCL clock input and attached to an I²C
controller master on the bus. Slave mode does not generate the SCL clock, but uses
the clock generated by the Master for the data transfers.
ID[x]
6
Input, analog
Device ID Address Select
Resistor to Ground and 10 kΩ pull-up to 1.8V rail. See Table 3
CONTROL AND CONFIGURATION
PDB
Power down Mode Input Pin.
9
Input, LVCMOS
w/ pull down
PDB = H, Serializer is enabled and is ON.
PDB = L, Serailizer is in Power Down mode. When the Serializer is in Power Down,
the PLL is shutdown, and IDD is minimized. Programmed control register data are
NOT retained and reset to default values
RES
7
Input, LVCMOS Reserved.
w/ pull down This pin MUST be tied LOW.
FPD-LINK III INTERFACE
DOUT+
13
Input/Output, Non-inverting differential output, bidirectional control channel input. The interconnect
CML
must be AC Coupled with a 100 nF capacitor.
DOUT-
12
Input/Output, Inverting differential output, bidirectional control channel input. The interconnect must
CML
be AC Coupled with a 100 nF capacitor.
POWER AND GROUND
VDDPLL
10
Power, Analog PLL Power, 1.8V ±5%
VDDT
11
Power, Analog Tx Analog Power, 1.8V ±5%
VDDCML
14
Power, Analog CML & Bidirectional Channel Driver Power, 1.8V ±5%
VDDD
28
Power, Digital Digital Power, 1.8V ±5%
VDDIO
VSS
25
DAP
Power, Digital
Ground, DAP
Power for I/O stage. The single-ended inputs and SDA, SCL are powered from V_DDIO.
V_DDIO can be connected to a 1.8V ±5% or 3.3V ±10%
DAP must be grounded. DAP is the large metal contact at the bottom side, located at
the center of the WQFN package. Connected to the ground plane (GND) with at least
9 vias.
4
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