DS90C387_15 Datasheet, PDF (6/33 Pages) Texas Instruments – Dual Pixel LVDS Display Interface (LDI)-SVGA/QXGA

DS90C387, DS90CF388
SNLS012H – MAY 2000 – REVISED APRIL 2013
Transmitter Switching Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Min
Typ
TPDD
Transmitter Powerdown Delay (Figure 10)
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Max
Unit
100
ns
Receiver Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Min
Typ
Max
Unit
CLHT
CMOS/TTL Low-to-High Transition Time (Figure 4), Rx data out
1.52
2.0
ns
CMOS/TTL Low-to-High Transition Time (Figure 4), Rx clock out
0.5
1.0
ns
CHLT
CMOS/TTL High-to-Low Transition Time (Figure 4), Rx data out
1.7
2.0
ns
CMOS/TTL High-to-Low Transition Time (Figure 4), Rx clock out
0.5
1.0
ns
RCOP
RCOH
RxCLK OUT Period (Figure 7)
RxCLK OUT High Time (Figure 7)⁽¹⁾
f = 112 MHz
8.928
T
3.5
25
ns
ns
f = 85 MHz
4.5
ns
RCOL
RxCLK OUT Low Time (Figure 7)⁽¹⁾
f = 112 MHz
3.5
ns
f = 85 MHz
4.5
ns
RSRC
RxOUT Setup to RxCLK OUT (Figure 7)⁽¹⁾
f = 112 MHz
2.4
ns
f = 85 MHz
3.0
ns
RHRC
RxOUT Hold to RxCLK OUT (Figure 7)⁽¹⁾
f = 112 MHz
3.4
ns
f = 85 MHz
4.75
ns
RPLLS Receiver Phase Lock Loop Set (Figure 9)
10
ms
RPDD
Receiver Powerdown Delay (Figure 11)
1
µs
(1) The Minimum and Maximum Limits are based on statistical analysis of the device performance over voltage and temperature ranges.
This parameter is functionally tested on Automatic Test Equipment (ATE). ATE is limited to 85MHz. A sample of characterization parts
have been bench tested to verify functional performance.
Chipset RSKM Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.^{(1) (2)}. See Applications Information
for more details on this parameter and how to apply it.
Symbol
Parameter
Min
Typ
Max
Unit
RSKM Receiver Skew Margin without Deskew in non-DC Balance
f = 112 MHz
170
ps
Mode, (Figure 12), ⁽³⁾
f = 100 MHz
170
240
ps
f = 85MHz
300
350
ps
f = 66MHz
300
350
ps
RSKM Receiver Skew Margin without Deskew in DC Balance Mode, f = 112 MHz
170
ps
(Figure 12)⁽³⁾
f = 100 MHz
170
200
ps
f = 85 MHz
250
300
ps
f = 66 MHz
250
300
ps
f = 50MHz
100
350
ps
f = 40MHz
94
530
ps
(1) The Minimum and Maximum Limits are based on statistical analysis of the device performance over voltage and temperature ranges.
This parameter is functionally tested on Automatic Test Equipment (ATE). ATE is limited to 85MHz. A sample of characterization parts
have been bench tested to verify functional performance.
(2) Typical values for RSKM and RSKMD are applicable for fixed V_CC and T _A for the Transmitter and Receiver (both are assumed to be at
the same V_CC and T _A points).
(3) Receiver Skew Margin (RSKM) is defined as the valid data sampling region at the receiver inputs. This margin takes into account
transmitter output pulse positions (min and max) and the receiver input setup and hold time (internal data sampling window - RSPOS).
This margin allows for LVDS interconnect skew, inter-symbol interference (both dependent on type/length of cable) and clock
jitter.RSKM ≥ cable skew (type, length) + source clock jitter (cycle to cycle, TJCC) + ISI (if any). See Applications Information for more
details.
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