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DS90C387_15 Datasheet, PDF (19/33 Pages) Texas Instruments – Dual Pixel LVDS Display Interface (LDI)-SVGA/QXGA
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DS90C387, DS90CF388
SNLS012H – MAY 2000 – REVISED APRIL 2013
NOTE: The LVDS Clock signal is also DC Balanced in this mode. The rising edge location is fixed, but the location of the
falling edge will be in one of two locations as shown above. Optional features supported: Pre-emphasis, and Deskew.
Figure 18. 48 Parallel TTL Data Inputs Mapped to LVDS Outputs
DC Balanced Mode - Data Enabled, BAL=High
Figure 19. Control Signals Transmitted During Blanking
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Product Folder Links: DS90C387 DS90CF388