DS90C387_15 Datasheet, PDF (11/33 Pages) Texas Instruments – Dual Pixel LVDS Display Interface (LDI)-SVGA/QXGA

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DS90C387, DS90CF388
SNLS012H – MAY 2000 – REVISED APRIL 2013
C — Setup and Hold Time (Internal data sampling window) defined by RSPOS (receiver input strobe position) min
and max
TPPOS — Transmitter output pulse position (min and max)
RSKM ≥ Cable Skew (type, length) + LVDS Source Clock Jitter (cycle to cycle) + ISI (Inter-symbol interference)
■ Cable Skew—typically 10 ps to 40 ps per foot, media dependent
■ TJCC — Cycle-to-cycle LVDS Output jitter (TJCC) is less than 100 ps (worse case estimate).
■ ISI is dependent on interconnect length; may be zero
See Applications Information for more details.
Figure 12. Receiver Skew Margin
C — Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and
max
RSKMD ≥ TPPOSvariance (d) + TJCC (output jitter)(f) + ISI (m)
■ d = Tppos — Transmitter output pulse position (min and max)
■ f = TJCC — Cycle-to-cycle LVDS Output jitter (TJCC) is less than 100 ps (worse case estimate).
■ m = extra margin - assigned to ISI in long cable applications
See Applications Information for more details.
Figure 13. Receiver Skew Margin (RSKMD) with DESKEW
Figure 14. TJCC Test Setup - DS90C387
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