DS90C387_15 Datasheet, PDF (23/33 Pages) Texas Instruments – Dual Pixel LVDS Display Interface (LDI)-SVGA/QXGA

DS90C387, DS90CF388
www.ti.com
SNLS012H – MAY 2000 – REVISED APRIL 2013
SUPPORT OF CNTLE, CNTLF
The 387/388 will also support the transmission of one or two additional user-defined control signals in the 'dual
pixel' DC Balanced output mode which are active during blanking while VSYNC is low. The additional control
signals, referred to as CNTLE and CNTLF, should be multiplexed with data signals and provided to the
transmitter inputs. Inputs B26 - CNTLF and B27 - CNTLE are designated for this purpose. When operating in 'DC
Balanced' mode, controls (CNTLE, CNTLF) are transmitted on LVDS channels A4 and A5 during the blanking
interval when VSYNC is low. CNTLE and CNTLF are sampled ONE (1) clock cycle after VSYNC transitions from
a HIGH to a LOW state. CNTLE and CNTLF are sampled on each cycle until VSYNC transitions from a LOW to
a HIGH, and they are then latched until the next VSYNC LOW cycle. Refer to Figure 20 for details. These signals
may be active only during blanking while VSYNC is low. Control signal levels are latched and held in the last
valid state when VSYNC transitions from low to high. These control signals are available as TTL outputs on the
receiver. CNTLE and CNTLF outputs on the DS90CF388 should be left as a no connect (NC) when not used.
Deskew
The OpenLDI receiver (DS90CF388) is able to tolerate a minimum of 300ps skew between the signals arriving
on a single differential pair (intra-pair) and a minimum of ±1 LVDS data bit time skew between signals arriving on
dependent differential pair (pair-to-pair). This is supported in the DC Balance data transmission mode only. Each
data channel is deskewed independently and is tuned with a step size of 1/3 of a bit time over a range of +/−1
TBIT. The Deskew feature operates up to clock rates of 80 MHz only. When using the DESKEW feature, the
sampling strobe will remain within the middle third of the LVDS sub symbol.To complete the deskew operation, a
minimum of four clock cycles is required during blanking time. This allows the chipset to support reduced
blanking applications.
Backwards Compatible Mode with FPD-Link
The transmitter provides a second LVDS output clock. Both LVDS clocks will be identical in 'Dual pixel mode'.
This feature supports backward compatibility with the previous generation of devices - the second clock allows
the transmitter to interface to panels using a 'dual pixel' configuration of two 24-bit or 18-bit 'notebook' receivers.
Note that redundant copies of certain signals are also sent. These signals are denoted with an * symbol, and are
shown in Figure 17. The DS90CF388 does not sample the bits show with an * symbol. If interfaceing with FPD-
Link Receivers, these signals may be recovered if desired.
Pre-emphasis feature is available for use in both the DC Balanced and non-DC Balanced (backwards
compatible) modes.
Transmitter Features
The transmitter is designed to reject cycle-to-cycle jitter which may be seen at the transmitter input clock. Very
low cycle-to-cycle jitter is passed on to the transmitter outputs. Cycle-to-cycle jitter has been measured over
frequency to be less than 100 ps with input step function jitter applied. This should be subtracted from the
RSKM/RSKMD budget as shown and described in Figure 12 and Figure 13. This rejection capability significantly
reduces the impact of jitter at the TXinput clock pin, and improves the accuracy of data sampling in the receiver.
Transmitter output jitter is effected by PLLVCC noise and input clock jitter - minimize supply noise and use a low
jitter clock source to limit output jitter. Timing and control signals (VSYNC, HSYNC, DE and two user-defined
signals) are sent during blanking intervals to ensure correct reception of these critical signals.
The transmitter is offered with programmable edge data strobes for convenient interface with a variety of
graphics controllers. The transmitter can be programmed for rising edge strobe or falling edge strobe through a
dedicated pin. A rising edge transmitter will inter-operate with a falling edge receiver without any translation logic.
RSKM - Receiver Skew Margin
RSKM is a chipset parameter and is explained in AN-1059 (SNLA050) in detail. It is the difference between the
transmitter’s pulse position and the receiver’s strobe window. RSKM must be greater than the summation of:
Interconnect skew, LVDS Source Clock Jitter (TJCC), and ISI (if any). See Figure 12. Interconnect skew includes
PCB traces differences, connector skew and cable skew for a cable application. PCB trace and connector skew
can be compensated for in the design of the system. Cable skew is media type and length dependant.
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