DS90C387_15 Datasheet, PDF (21/33 Pages) Texas Instruments – Dual Pixel LVDS Display Interface (LDI)-SVGA/QXGA

DS90C387, DS90CF388
www.ti.com
APPLICATIONS INFORMATION
SNLS012H – MAY 2000 – REVISED APRIL 2013
HOW TO CONFIGURE THE DS90C387 AND DS90CF388 FOR MOST COMMON APPLICATION
1. To configure for single input pixel-to-dual pixel output application, the DS90C387 “DUAL” pin must be set to
1/2 Vcc=1.65V. This may be implemented using pull-up and pull-down resistors of 10kΩ each as shown in
Figure 16. A capacitor between “DUAL” pin and ground will help to stabilize the DC voltage level in a noisy
environment. In this configuration, the input signals (single pixel) are split into odd and even pixel (dual
pixels) starting with the odd (first) pixel outputs A0-to-A3 the next even (second) pixel outputs to A4-to-A7.
The splitting of the data signal also starts with DE (data enable) transitioning from logic low to high indicating
active data. The "R_FDE" pin must be set high in this case. This is supported in DC Balanced and non-DC
Balanced (BAL=low or high) data transmission. The number of clock cycles during blanking must be an
EVEN number. This configuration will allow the user to interface to an LDI receiver (DS90CF388) or if in the
non-DC Balanced mode (BAL=low) then two FPD-Link 'notebook' receivers (DS90CF384A). The DC Balance
feature is recommended for monitor applications which require >2meters of cable length. Notebook
applications should disable this feature to reduce the current consumption of the chipset. Note that only the
DS90C387/DS90CF388 support the DC Balance data transmission feature.
2. To configure for single pixel or dual pixel application using the DS90C387/DS90CF388, the “DUAL” pin must
be set to Vcc (dual) or Gnd (single). In dual mode, the transmitter-DS90C387 has two LVDS clock outputs
enabling an interface to two FPD-Link 'notebook' receivers (DS90CF384A or DS90CF386). In single mode,
outputs A4-to-A7 and CLK2 are disabled which reduces power dissipation. Both single and dual mode also
support the DC Balance data transmission feature, which should only be used for monitor application.
3. The DS90CF388 is able to support single or dual pixel interface up to 112MHz operating frequency. This
receiver may also be used to interface to a VGA controller with an integrated LVDS transmitter without DC
Balance data transmission. In this case, the receivers “BAL” pin must be tied low (DC Balance disabled).
NEW FEATURES DESCRIPTION
Pre-Emphasis
Adds extra current during LVDS logic transition to reduce the cable loading effects. Pre-emphasis strength is set
via a DC voltage level applied from min to max (0.75V to Vcc) at the “PRE” pin. A higher input voltage on the
”PRE” pin increases the magnitude of dynamic current during data transition. The “PRE” pin requires one pull-up
resistor (Rpre) to Vcc in order to set the DC level. There is an internal resistor network, which cause a voltage
drop. See Table 5 and Table 6 to set the voltage level.
Table 5. PRE-EMPHASIS DC VOLTAGE LEVEL WITH
(RPRE) ⁽¹⁾
Rpre
1MΩ or NC
50kΩ
9kΩ
3kΩ
1kΩ
100Ω
Resulting PRE
Voltage
0.75V
1.0V
1.5V
2.0V
2.6V
Vcc
Effects
Standard LVDS
50% pre-emphasis
100% pre-emphasis
(1) This is based on testing with standard shield twisted pair cable. The
amount of pre-emphasis will vary depending on the type of cable,
length and operating frequency.
Table 6. PRE-EMPHASIS NEEDED PER CABLE
LENGTH
Frequency
112MHz
112MHz
80MHz
80MHz
PRE Voltage
1.0V
1.5V
1.0V
1.2V
Typical cable length
2 meters
5 meters
2 meters
7 meters
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