DS90C387_15 Datasheet, PDF (2/33 Pages) Texas Instruments – Dual Pixel LVDS Display Interface (LDI)-SVGA/QXGA

DS90C387, DS90CF388
SNLS012H – MAY 2000 – REVISED APRIL 2013
Transmitter Block Diagram
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Receiver Block Diagram
A0
A1
A2
A3
A4
A5
A6
A7
CLK
DESKEW
PLL
CMOS/TTL OUTPUTS
8 _RED1
8
GRN1
8 _BLU1
8 _RED2
8
GRN2
8 _BLU2
FPLINE (HSYNC)
FPFRAME (VSYNC)
DRDY (Data Enable)
POWER DOWN
SHFCLKOUT
(40 to 112 MHz)
Generalized Block Diagram
CMOS/TTL INPUTS
RED1 ⁸
GRN1 ⁸
BLU1 ⁸
RED2 ⁸
GRN2 ⁸
BLU2 ⁸
FPLINE (HSYNC)
FPFRAME (VSYNC)
DRDY (Data Enable)
FPSHIFT IN
(TRANSMIT CLOCK IN)
(40 to 112 MHz)
POWER DOWN
DATA (LVDS)
(280 to 672 Mbit/s
On Each LVDS
Channel)
CLOCK (LVDS)
(40 to 112 MHz)
PLL
DS90C387VJD
CMOS/TTL OUTPUTS
8
RED1
8
GRN1
8
BLU1
8
RED2
8
GRN2
8
BLU2
FPLINE (HSYNC)
FPFRAME (VSYNC)
DRDY (Data Enable)
PLL
DS90CF388VJD
FPSHIFT OUT
(40 to 112 MHz)
POWER DOWN
2
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