DS90C387_15 Datasheet, PDF (13/33 Pages) Texas Instruments – Dual Pixel LVDS Display Interface (LDI)-SVGA/QXGA

DS90C387, DS90CF388
www.ti.com
SNLS012H – MAY 2000 – REVISED APRIL 2013
Pin Name
Rn, Gn, Bn, DE,
HSYNC, VSYNC
AnP
AnM
CLKIN
R_FB
R_FDE
CLK1P
CLK1M
PD
PLLSEL
BAL
DS90C387 PIN DESCRIPTIONS — FPD LINK TRANSMITTER
I/O No.
Description
I
51 TTL level input. This includes: 16 Red, 16 Green, 16 Blue, and 3 control lines HSYNC, VSYNC, DE
(Data Enable).⁽¹⁾
O
8 Positive LVDS differential data output.
O
8 Negative LVDS differential data output.
I
1 TTL level clock input.
I
1 Programmable data strobe select. Rising data strobe edge selected when input is high. ⁽¹⁾
I
1 Programmable control (DE) strobe select. Tied high for data active when DE is high. ⁽¹⁾
O
1 Positive LVDS differential clock output.
O
1 Negative LVDS differential clock output.
I
1 TTL level input. Assertion (low input) tri-states the outputs, ensuring low current at power down. ⁽¹⁾
I
1 PLL range select. This pin must be tied to V_CC for auto-range. NC or tied to Ground is reserved for
future use. Typical shift point is between 55 and 68 MHz. ^{(1) (2)}
I
1 Mode select for DC Balanced (new) or non-DC Balanced (backward compatible) interface. DC
Balance is active when input is high. NC or tied to Ground, the DC Balance function is disabled. ⁽¹⁾
(3) (4)
PRE
DUAL
V_CC
GND
PLLV_CC
PLLGND
LVDSV_CC
LVDSGND
CLK2P/NC
CLK2M/NC
I
1 Pre-emphasis level select. Pre-emphasis is active when input is tied to V_CC through external pull-up
resistor. Resistor value determines pre-emphasis level (see Pre-Emphasis). For normal LVDS drive
level (No pre-emphasis) leave this pin open (do not tie to ground).⁽¹⁾
I
1 Three-mode select for dual pixel, single pixel, or single pixel input to dual pixel output operation.
Single pixel mode when input is low (only LVDS channels A0 thru A3 and CLK1 are active) for power
savings. Dual mode is active when input is high. Single in - dual out when input is at 1/2 Vcc. ⁽¹⁾
Figure 16
I
4 Power supply pins for TTL inputs and digital circuitry.
I
5 Ground pins for TTL inputs and digital circuitry.
I
2 Power supply pin for PLL circuitry.
I
3 Ground pins for PLL circuitry.
I
3 Power supply pin for LVDS outputs.
I
4 Ground pins for LVDS outputs.
O
1 Additional positive LVDS differential clock output. Identical to CLK1P. No connect if not used.
O
1 Additional negative LVDS differential clock output. Identical to CLK1M. No connect if not used.
(1) Inputs default to “low” when left open due to internal pull-down resistor.
(2) The PLL range shift point is in the 55 - 68 MHz range, typically the shift will occur during the lock time.
(3) DC Balancing is functionally tested on Automatic Test Equipment (ATE) at 85 MHz only. A sample of characterization units have been
bench tested at 112 MHz to verify full speed performance.
(4) The DS90CF388 is designed to automatically detect the DC Balance or non-DC Balance transmitted data from the DS90C387 and
deserialize the LVDS data according to the defined bit mapping.
Pin Name
AnP
AnM
Rn, Gn, Bn, DE,
HSYNC, VSYNC
RxCLK INP
RxCLK INM
RxCLK OUT
R_FDE
PLLSEL
DS90CF388 PIN DESCRIPTIONS — FPD LINK RECEIVER
I/O No.
Description
I
8 Positive LVDS differential data inputs.
I
8 Negative LVDS differential data inputs.
O
51 TTL level data outputs. This includes: 16 Red, 16 Green, 16 Blue, and 3 control lines— HSYNC (LP),
VSYNC (FLM), DE (Data Enable).
I
1 Positive LVDS differential clock input.
I
1 Negative LVDS differential clock input.
O
1 TTL level clock output. The falling edge acts as data strobe.
I
1 Programmable control (DE) strobe select. Tied high for data active when DE is high. ⁽¹⁾
I
1 PLL range select. This pin must be tied to V_CC for auto-range. NC or tied to Ground is reserved for
future use. Typical shift point is between 55 and 68 MHz. ^{(2) (3)}
(1) Inputs default to “low” when left open due to internal pull-down resistor.
(2) DC Balancing is functionally tested on Automatic Test Equipment (ATE) at 85 MHz only. A sample of characterization units have been
bench tested at 112 MHz to verify full speed performance.
(3) The PLL range shift point is in the 55 - 68 MHz range, typically the shift will occur during the lock time.
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