DS90C387_15 Datasheet, PDF (22/33 Pages) Texas Instruments – Dual Pixel LVDS Display Interface (LDI)-SVGA/QXGA

DS90C387, DS90CF388
SNLS012H – MAY 2000 – REVISED APRIL 2013
Table 6. PRE-EMPHASIS NEEDED PER CABLE
LENGTH (continued)
Frequency
65MHz
56MHz
PRE Voltage
1.5V
1.0V
Typical cable length
10 meters
10 meters
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DC Balance
In the Balanced operating modes, in addition to pixel and control information an additional bit is transmitted on
every LVDS data signal line during each cycle of active data as shown in Figure 18. This bit is the DC Balance
bit (DCBAL). The purpose of the DC Balance bit is to minimize the short- and long-term DC bias on the signal
lines. This is achieved by selectively sending the pixel data either unmodified or inverted.
The value of the DC Balance bit is calculated from the running word disparity and the data disparity of the current
word to be sent. The data disparity of the current word shall be calculated by subtracting the number of bits of
value 0 from the number of bits value 1 in the current word. Initially, the running word disparity may be any value
between +7 and −6. The running word disparity shall be calculated as a continuous sum of all the modified data
disparity values, where the unmodified data disparity value is the calculated data disparity minus 1 if the data is
sent unmodified and 1 plus the inverse of the calculated data disparity if the data is sent inverted. The value of
the running word disparity shall saturate at +7 and −6.
The value of the DC Balance bit (DCBAL) shall be 0 when the data is sent unmodified and 1 when the data is
sent inverted. To determine whether to send pixel data unmodified or inverted, the running word disparity and the
current data disparity are used. If the running word disparity is positive and the current data disparity is positive,
the pixel data shall be sent inverted. If the running word disparity is positive and the current data disparity is zero
or negative, the pixel data shall be sent unmodified. If the running word disparity is negative and the current data
disparity is positive, the pixel data shall be sent unmodified. If the running word disparity is negative and the
current data disparity is zero or negative, the pixel data shall be sent inverted. If the running word disparity is
zero, the pixel data shall be sent inverted.
Cable drive is enhanced with a user selectable pre-emphasis feature that provides additional output current
during transitions to counteract cable loading effects. DC balancing on a cycle-to-cycle basis, is also provided to
reduce ISI (Inter-Symbol Interference). With pre-emphasis and DC balancing, a low distortion eye-pattern is
provided at the receiver end of the cable. These enhancements allow cables 5 to 10+ meters in length to be
driven.
CONTROL SIGNAL SENT DURING BLANKING (DC BALANCE MODE)
The data enable control signal (DE) is used in the DC Balanced mode to distinguish between pixel data and
control information being sent. It must be continuously available to the device in order to correctly separate pixel
data from control information. For this reason, DE shall be sent on the clock signals, LVDS CLK1 and CLK2,
when operating in the DC Balanced mode. If the value of the control to be sent is 1 (active display), the value of
the control word sent on the clock signals shall be 1111000 or 1110000. If the value of the control to be sent is 0
(blanking time), the value of the control word sent on the clock signals shall be 1111100 or 1100000. This is true
when R_FDE=High. See Transmitter Pin Descriptions and Receiver Pin Descriptions.
The control information, such as HSYNC and VSYNC, is always sent unmodified. The value of the control word
to send is determined by the running word disparity and the value of the control to be sent. If the running word
disparity is positive and the value of the control to be sent is 0, the control word sent shall be 1110000. If the
running word disparity is zero or negative and the control word to be sent is 0, the control word sent shall be
1111000. If the running word disparity is positive and the value of the control to be sent is 1, the control word
sent shall be 1100000. If the running word disparity is zero or negative and the value of the control to be sent is
1, the control word sent shall be 1111100. The DC Balance bit shall be sent as 0 when sending control
information during blanking time. See Figure 19.
RGB outputs on the DS90CF388 are forced LOW during the blanking time.
Note that in the backward compatible mode (BAL=low) control and data is sent as regular LVDS data. See
Figure 17.
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