BQ33100_15 Datasheet, PDF (57/67 Pages) Texas Instruments – Super Capacitor Manager

www.ti.com
11 Layout
bq33100
SLUS987B – JANUARY 2011 – REVISED DECEMBER 2015
11.1 Layout Guidelines
A capacitance monitor circuit board is a challenging environment due to the fundamental incompatibility of high
current traces and ultra-low current semiconductor devices. The best way to protect against unwanted trace-to-
trace coupling is with a component placement, where the high-current section is on the opposite side of the
board from the electronic devices. Every attempt must be made to route high-current traces away from signal
traces, which enter the bq33100 directly. IC references and registers can be disturbed and in rare cases
damaged due to magnetic and capacitive coupling from the high-current path.
NOTE
During surge current and ESD events, the high-current traces appear inductive and can
couple unwanted noise into sensitive nodes of the gas gauge electronics.
The learning load components can become heated depending on the component values selected. TI
recommends that any heat is dissipated away from the bq33100 to ensure its maxim operating temperature is
not exceeded.
11.2 Layout Example
bq33100
Learning load circuit
with extra copper for
heat dissipation
Figure 20. bq33100 Board Layout
Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: bq33100
Submit Documentation Feedback
57