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| BQ33100_15 Datasheet, PDF (10/67 Pages) Texas Instruments – Super Capacitor Manager | |||
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bq33100
SLUS987B â JANUARY 2011 â REVISED DECEMBER 2015
www.ti.com
7.21 Timing Requirements: SMBus
Typical values stated where TA = 25°C and VCC = VCC = 14.4 V, Minimum and maximum values stated where TA = â40°C to
85°C and VCC = VCC = 3.8 V to 25 V (unless otherwise noted)
MIN
NOM
MAX UNIT
fSMB
fMAS
tBUF
tHD:STA
tSU:STA
tSU:STO
tHD:DAT
SMBus operating frequency
SMBus master clock frequency
Bus free time between start and stop
Hold time after (repeated) start
Repeated start setup time
Stop setup time
Data hold time
Slave mode, SCL 50% duty cycle
Master mode, no clock low slave extend
Receive mode
Transmit mode
10
51.2
4.7
4
4.7
4
0
300
100 kHz
kHz
μs
μs
μs
μs
ns
tSU:DAT
tTIMEOUT
tLOW
tHIGH
tLOW:SEXT
Data setup time
Error signal and detect
Clock low period
Clock high period
Cumulative clock low slave extend
time
See (1)
See (2)
See (3)
250
ns
25
35 ms
4.7
μs
4
50 μs
25 ms
tLOW:MEXT
tF
tR
Cumulative clock low master extend
time
Clock and data fall time
Clock and data rise time
See (4)
See (5)
See (6)
10 ms
300 ns
1000 ns
(1) The bq33100 times out when any clock low exceeds tTIMEOUT
(2) tHIGH maximum is the minimum bus idle time. SCL = SDA = 1 for t > 50 μs causes reset of any transaction involving bq33100 that is in
progress.
(3) tLOW:SEXT is the cumulative time a slave device is allowed to extend the clock cycles in one message from initial start to the stop.
(4) tLOW:MEXT is the cumulative time a master device is allowed to extend the clock cycles in one message from initial start to the stop.
(5) Rise time tR = VILMAX â 0.15) to (VIHMIN + 0.15)
(6) Fall time tF = 0.9VDD to (VILMAX â 0.15)
SCL
t LOW
tR
tF
t HD:STA
SDATA
P
t HD:STA
t HD:DAT
t HIGH
t SU:STA
t SU:DAT
t SU:STO
t
BUF
S
S
P
Figure 1. SMBus Timing
SCL
Start
t LOW:MEXT
t LOW:SEXT
SCLACK 1
t LOW:MEXT
Stop
SCLACK 1
t LOW:MEXT
SDATA
Figure 2. SMBus tTIMEOUT
10
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