BQ33100_15 Datasheet, PDF (17/67 Pages) Texas Instruments – Super Capacitor Manager

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bq33100
SLUS987B – JANUARY 2011 – REVISED DECEMBER 2015
Feature Description (continued)
8.3.2 Capacitor Voltage Balancing
Capacitor voltage balancing in the bq33100 is accomplished by connecting an external parallel bypass load to
each capacitor, and enabling the bypass load depending on each individual capacitors voltage level. The bypass
load is typically formed by a P-ch MOSFET and a resistor connected in series across each capacitor. The filter
resistors that connect the capacitor tabs to VC1 to approximately VC4 pins of the bq33100 are required to be 1 k
ohms to support this function on all capacitors other than the lowest. The lowest capacitor bypass is enabled
through the VC5BAL pin. Capacitor Voltage Balancing is only operational after the ManufacturerAccess Lifetime
and Capacitor Balancing Enable (0x21) command is sent to the bq33100.
Using this circuit, the bq33100 balances the capacitors during charge and after charge termination by
discharging those capacitors with voltage above the threshold set in CB Threshold and if the ΔV in capacitor
voltages exceeds the value programmed in CB Min. During capacitor voltage balancing, the bq33100 measures
the capacitor voltages periodically (during which time the voltage balancing circuit is turned off) and based on the
capacitor voltages, the bq33100 selects the appropriate capacitor to discharge. When ΔV of
CapacitorVoltage5...1 < CB Min then capacitor voltage balancing stops. Capacitor voltage balancing restarts
when ΔV of CapacitorVoltage5...1 ≥ CB Restart to avoid balancing start-stop oscillations.
Capacitor voltage balancing only occurs when:
• Charging current is detected (Current > Chg Current Threshold OR
• The [FC] flag in OperationStatus has been set AND
• ΔCapacitorVoltage5...1 ≥ CB Restart
Capacitor voltage balancing stops when:
• ΔCapacitorVoltage5...1 < CB Min
• Discharging current detected (Current > Dsg Current Threshold)
This feature is disabled when in Stack mode, when Operation Cfg [STACK ] =1.
8.3.3 Charge Control
The bq33100 supports two main charge control architectures, discrete control and smart control. In a discrete
charge control implementation the CHGLVL0 and CHGLVL1 pins can be used to adjust the charging voltage of
an external supply (see reference schematic for example).
As the super capacitors age a higher charging voltage can be configured to offset the deteriorating super
capacitor ESR and Capacitance due to aging. With the discrete control method there are 4 levels of charging
voltages that can be chosen, V Chg Nominal, V Chg A, V Chg B and V Chg Max. The setting of the charging
voltage is determined by the value of the latest determined required Charging Voltage.
The CHGLVL0 and CHGLVL1 pin states are defined by the V Chg X parameters selected per Table 2:
CHARGINGVOLTAGE
V Chg Nominal
V Chg A
V Chg B
V Chg Max
Table 2. ChargingVoltage Parameters
CHGLVL1 (PIN 12)
0
0
1
1
CHGLVL0 (PIN11)
0
1
0
1
In a smart control architecture the bq33100 makes the appropriate maximum charging current and charging
voltage per the charging algorithm available through the ChargingCurrent and ChargingVoltage SMBus
commands respectively. This enables either an SMBus master or smart charger to manage the charging of the
super capacitor pack.
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