BQ33100_15 Datasheet, PDF (14/67 Pages) Texas Instruments – Super Capacitor Manager

bq33100
SLUS987B – JANUARY 2011 – REVISED DECEMBER 2015
8.2 Functional Block Diagram
CHG
SDA SCL _LVL1
CHG
LVL0
LLEN
CHG
REG27
Serial
Communications
System Control
Data Flash
Memory
Regulator
Oscillator
Voltage
Measurement
www.ti.com
CHGOR
FET Drive
VCC VCCPACK
RBI
Power Mode
Control
GND
AFE HW
Control
VC1
Watchdog
VC2
Cell Voltage Mux
& Translation
Charging
Algorithm
Over
Temperature
Protection
Temperature
Measurement
Over- &
Under-
Voltage
Protection
Over
Current
Protection
SuperCap
Management
Coloumb
Counter
External Cell
Balancing Driver
HW Over
Current &
Short Circuit
Protection
VC4
VC5
VC5BAL
TS
SRN SRP
8.3 Feature Description
8.3.1 Capacitance Monitoring and Learning
8.3.1.1 Monitoring and Control Operational Overview
The bq33100 periodically determines the capacitance and equivalent series resistance (ESR) of the super
capacitor array during normal operation. The Learning Frequency is a register that sets the time between
automatic learning cycles of the Super Capacitor which can also be manually executed by issuing a Learn
command. The bq33100 uses the learning cycles to update the Capacitance and ESR registers accordingly and
both are accessible through the SMBus interface.
Learning process is a multi-step procedure fully controlled by the bq33100 that will perform the following
sequence to learn Capacitance and ESR:
1. Charge to V Learn Max
2. Discharge using constant current load to a minimum voltage of the present charging voltage and internally
record voltage and time
3. Charge to V Learn Max
4. Discharge using constant current load and internally record current and time
5. Calculate Capacitance and ESR based on recorded voltage and current
6. Determine new Charging Voltage
14
Submit Documentation Feedback
Product Folder Links: bq33100
Copyright © 2011–2015, Texas Instruments Incorporated