THS10064_09 Datasheet, PDF (5/42 Pages) Texas Instruments – 10-BIT, 4 ANALOG INPUT, 6 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER

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THS10064
SLAS255B – DECEMBER 1999 – REVISED DECEMBER 2002
TIMING SPECIFICATION OF THE SINGLE CONVERSION MODE^{(1) (2)}
PARAMETER
TEST CONDITIONS
tc
Clock cycle of the internal clock oscillator
1 analog input
t1
Pulse duration, CONVST
2 analog inputs
3 analog inputs
4 analog inputs
td(A)
Aperture time
1 analog input
td2
Delay time between consecutive start of single ^{2 analog inputs}
conversion
3 analog inputs
4 analog inputs
1 analog input, TL = 1
Delay time, DATA_AV becomes active for the ^{2 analog inputs, TL = 2}
trigger level condition: TRIG0 = 0, TRIG1 = 0 _{3 analog inputs, TL = 3}
4 analog inputs, TL = 4
1 analog input, TL = 4
td(DATA_AV)
Delay time, DATA_AV becomes active for the
trigger level condition: TRIG0 = 1, TRIG1 = 0
2 analog inputs, TL = 4
3 analog inputs, TL = 6
4 analog inputs, TL = 8
1 analog input, TL = 8
Delay time, DATA_AV becomes active for the ^{2 analog inputs, TL = 8}
trigger level condition: TRIG0 = 0, TRIG1 = 1 _{3 analog inputs, TL = 9}
4 analog inputs, TL = 12
td(DATA_AV)
Delay time, DATA_AV becomes active for the
trigger level condition: TRIG0 = 1, TRIG1 = 1
(1) _{Timing parameters are ensured by design but are not tested.}
(2) _{See Figure 26.}
1 analog input, TL = 14
2 analog inputs, TL = 12
3 analog inputs, TL = 12
MIN
151
1.5×tc
2.5×tc
3.5×tc
4.5×tc
2×tc
3×tc
4×tc
5×tc
TYP
MAX
167
175
UNIT
ns
ns
1
ns
ns
6.5×tc + 15
7.5×tc +15
ns
8.5×tc +15
9.5×tc +15
3×t2 +6.5×tc+15
t2 +7.5×tc+15
ns
t2 +8.5×tc+15
t2 +9.5×tc+15
7×t2 +6.5×tc+15
3×t2 +7.5×tc+15
ns
2×t2 +8.5×tc+15
2×t2 +9.5×tc+15
13×t2 +6.5×tc+15
5×t2 +7.5×tc+15 ns
3×t2 +8.5×tc+15
PIN ASSIGNMENTS
DA (TSSOP) PACKAGE
(TOP VIEW)
D0 ₁
D1 ₂
D2 3
D3 4
D4 5
D5 6
BV_DD 7
BGND 8
D6 9
D7 10
D8 11
D9 12
RA0 13
RA1 14
CONV_CLK (CONVST) 15
DATA_AV 16
32 ^AINP
31 ^AINM
30 BINP
29 BINM
28 REFIN
27 REFOUT
26 REFP
25 REFM
24 AGND
23 AV_DD
22 CS0
21 CS1
20 WR (R/W)
19 RD
18 DV_DD
17 DGND
5