THS10064_09 Datasheet, PDF (29/42 Pages) Texas Instruments – 10-BIT, 4 ANALOG INPUT, 6 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER

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THS10064
SLAS255B – DECEMBER 1999 – REVISED DECEMBER 2002
Read Timing Parameter (CS0-controlled)^†
PARAMETER
tsu(R/W)
ta
td(CSDAV)
th
th(R/W)
tw(CS)
† _{CS = CS0}
Setup time, R/W high to last CS valid
Access time, last CS valid to data valid
Delay time, last CS valid to DATA_AV inactive
Hold time, first CS invalid to data invalid
Hold time, first external CS invalid to R/W change
Pulse duration, CS active
MIN TYP MAX UNIT
0
ns
0
10 ns
12
ns
0
5 ns
5
ns
10
ns
Write Timing (using R/W, CS0-controlled)
Figure 39 shows the write-timing behavior when the WR(R/W) input is programmed as a combined read-write input
R/W. The RD input has to be tied to high-level in this configuration. This timing is called CS0-controlled because CS0
is the last external signal of CS0, CS1, and R/W which becomes valid.
tw(CS)
CS0
10%
10%
90%
CS1
tsu(R/W)
ÓÓÓÓÓÓÓÓÓÓÓÓ _WR
th(R/W) _{ÓÓÓÓÓÓÓÓÓ}
RD
D(0–9)
tsu
90%
th
90%
DATA_AVÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖ
Figure 39. Write Timing Diagram Using R/W (CS0-controlled)
Read Timing Parameter (CS0-controlled)^†
PARAMETER
tsu(R/W)
tsu
th
th(R/W)
tw(CS)
† _{CS = CS0}
Setup time, R/W stable to last CS valid
Setup time, data valid to first CS invalid
Hold time, first CS invalid to data invalid
Hold time, first CS invalid to R/W change
Pulse duration, CS active
MIN TYP MAX UNIT
0
ns
5
ns
2
ns
5
ns
10
ns
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