THS10064_09 Datasheet, PDF (21/42 Pages) Texas Instruments – 10-BIT, 4 ANALOG INPUT, 6 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER

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THS10064
SLAS255B – DECEMBER 1999 – REVISED DECEMBER 2002
READING DATA FROM THE FIFO
The THS10064 informs the connected processor via the digital output DATA_AV (data available) that a block of
conversion values are ready to be read. The block size to be read is always equal to the setting of the trigger level.
The selectable trigger levels depend on the number of selected analog input channels. For example, when choosing
one analog input, a trigger level of 1, 4, 8, and 14 can be selected. The following figures demonstrate the principle
of reading the data (the READ signal is asynchronous to CONV_CLK).
In Figure 32, a trigger level of 1 is selected. The control signal DATA_AV is set to an active low pulse. This means
that the connected processor has the task to read 1 value from the ADC after every DATA_AV low pulse.
CONV_CLK
DATA_AV
READ
Figure 32. Trigger Level 1 Selected
In Figure 33, a trigger level of 4 is selected. The control signal DATA_AV is set to an active low pulse. This means
that the connected processor has the task to read 4 values from the ADC after every DATA_AV low pulse.
CONV_CLK
DATA_AV
READ
Figure 33. Trigger Level 4 Selected
In Figure 34, a trigger level of 8 is selected. The control signal DATA_AV is set to an active low pulse. This means
that the connected processor has the task to read 8 values from the ADC after every DATA_AV low pulse.
CONV_CLK
DATA_AV
READ
Figure 34. Trigger Level 8 Selected
In Figure 35, a trigger level of 14 is selected. The control signal DATA_AV is set to an active low pulse. This means
that the connected processor has the task to read 14 values from the ADC after every DATA_AV low pulse.
CONV_CLK
DATA_AV
READ
Figure 35. Trigger Level 14 Selected
READ is always the logical combination of CS0, CS1 and RD.
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