THS10064_09 Datasheet, PDF(27/42 Page) Texas Instruments – 10-BIT, 4 ANALOG INPUT, 6 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER

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THS10064_09 Datasheet, PDF (27/42 Pages) Texas Instruments – 10-BIT, 4 ANALOG INPUT, 6 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER

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THS10064

SLAS255B â DECEMBER 1999 â REVISED DECEMBER 2002

Table 13 shows four different programmable trigger levels for each configuration. The FIFO trigger level, which can

be selected, is dependent on the number of input channels. Both, a differential or a single-ended input is considered

as one channel. The processor therefore always reads the data from the FIFO in the same order and is able to

distinguish between the channels.

BIT 3

TRIG1

BIT 2

TRIG0

Table 13. FIFO Trigger Level

TRIGGER LEVEL

FOR 1 CHANNEL

(ADC values)

TRIGGER LEVEL

FOR 2 CHANNELS

(ADC values)

TRIGGER LEVEL

FOR 3 CHANNEL

(ADC values)

TRIGGER LEVEL

FOR 4 CHANNELS

(ADC values)

Reserved

TIMING AND SIGNAL DESCRIPTION OF THE THS10064

The reading from the THS10064 and writing to the THS10064 is performed by using the chip select inputs (CS0,

CS1), the write input WR and the read input RD. The write input is configurable to a combined read/write input (R/W).

This is desired in cases where the connected processor consists of a combined read/write output signal (R/W). The

two chip select inputs can be used to interface easily to a processor.

Reading from the THS10064 takes place by an internal RDint signal, which is generated from the logical combination

of the external signals CS0, CS1 and RD (see Figure 37). This signal is then used to strobe the words out of the FIFO

and to enable the output buffers. The last external signal (either CS0, CS1 or RD) to become valid makes RDint active

while the write input (WR) is inactive. The first of those external signals going to its inactive state then deactivates

RDint again.

Writing to the THS10064 takes place by an internal WRint signal, which is generated from the logical combination

of the external signals CS0, CS1 and WR. This signal is then used to strobe the control words into the control registers

0 and 1. The last external signal (either CS0, CS1 or WR) to become valid makes WRint active while the read input

(RD) is inactive. The first of those external signals going to its inactive state then deactivates WRint again.

CS0

Read Enable

CS1

Write Enable

Data Bits

Control/Data

Registers

Figure 37. Logical Combination of CS0, CS1, RD, and WR

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