THS10064_09 Datasheet, PDF (4/42 Pages) Texas Instruments – 10-BIT, 4 ANALOG INPUT, 6 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER

THS10064
SLAS255B – DECEMBER 1999 – REVISED DECEMBER 2002
www.ti.com
ELECTRICAL CHARACTERISTICS
over recommended operating conditions, VREF = internal, fs = 6 MHz, fI = 2 MHz at –1 dBFS (unless otherwise noted)
AC SPECIFICATIONS, AVDD =5 V, BVDD = DVDD = 3.3 V, CL < 30 pF
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
SINAD Signal-to-noise ratio + distortion
Differential mode
56
59
dB
Single-ended mode(1)
55
59
dB
SNR Signal-to-noise ratio
Differential mode
59
61
dB
Single-ended mode(1)
58
60
dB
THD Total harmonic distortion
Differential mode
Single-ended mode
–64 –61 dB
–63 –60 dB
ENOB
(SNR) ^{Effective number of bits}
Differential mode
9 9.5
Bits
Single-ended mode(1)
8.85 9.35
Bits
SFDR Spurious free dynamic range
Differential mode
Single-ended mode
61
65
dB
60
64
dB
Analog Input
Full-power bandwidth with a source impedance of 150 Ω in
differential configuration.
Full scale sinewave, –3 dB
96
MHz
Full-power bandwidth with a source impedance of 150 Ω in
single-ended configuration.
Full scale sinewave, –3 dB
54
MHz
Small-signal bandwidth with a source impedance of 150 Ω in
differential configuration.
100 mVpp sinewave, –3 dB
96
MHz
Small-signal bandwidth with a source impedance of 150 Ω in
single-ended configuration.
100 mVpp sinewave, –3 dB
54
MHz
(1) _{The SNR (ENOB) and SINAD is degraded typically by 2 dB in single-ended mode when the reading of data is asynchronous to the sampling}
clock.
TIMING SPECIFICATIONS⁽¹⁾
AVDD = 5 V, DVDD = BVDD = 3.3 V, VREF = internal, CL < 30 pF
PARAMETER
td(DATA_AV)
td(o)
Delay time
Delay time
tpipe
Latency
(1) _{See Figure 27.}
TEST CONDITIONS
MIN TYP MAX UNIT
5
ns
5
ns
CONV
5
CLK
4