SN74ALVC3631_07 Datasheet, PDF (5/29 Pages) Texas Instruments – SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES

SN74ALVC3631, SN74ALVC3641, SN74ALVC3651
512 × 36, 1024 × 36, 2048 × 36
SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SDMS025B – OCTOBER 1999 – REVISED JUNE 2000
Terminal Functions
TERMINAL
NAME
I/O
DESCRIPTION
A0–A35
I/O Port-A data. The 36-bit bidirectional data port for side A.
AE
O
Almost-empty flag. Programmable flag synchronized to CLKB. AE is low when the number of words in the FIFO is less
than or equal to the value in the almost-empty offset register (X).
Almost-full flag. Programmable flag synchronized to CLKA. AF is low when the number of empty locations in the FIFO
AF
O
is less than or equal to the value in the almost-full offset register (Y).
B0–B35
I/O Port-B data. The 36-bit bidirectional data port for side B.
CLKA
I
Port-A clock. CLKA is a continuous clock that synchronizes all data transfers through port A and can be asynchronous
or coincident to CLKB. IR and AF are synchronous to the low-to-high transition of CLKA.
CLKB
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Port-B clock. CLKB is a continuous clock that synchronizes all data transfers through port B and can be asynchronous
or coincident to CLKA. OR and AE are synchronous to the low-to-high transition of CLKB.
CSA
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Port-A chip select. CSA must be low to enable a low-to-high transition of CLKA to read or write data on port A. The
A0–A35 outputs are in the high-impedance state when CSA is high.
CSB
I
Port-B chip select. CSB must be low to enable a low-to-high transition of CLKB to read or write data on port B. The
B0–B35 outputs are in the high-impedance state when CSB is high.
ENA
I
Port-A master enable. ENA must be high to enable a low-to-high transition of CLKA to read or write data on port A.
ENB
I
Port-B master enable. ENB must be high to enable a low-to-high transition of CLKB to read or write data on port B.
FS1/SEN,
FS0/SD
Flag-offset select 1/serial enable, flag-offset select 0/serial data. FS1/SEN and FS0/SD are dual-purpose inputs used
for flag-offset-register programming. During a device reset, FS1/SEN and FS0/SD select the flag-offset programming
method. Three offset-register programming methods are available: automatically load one of two preset values,
parallel load from port A, and serial load.
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When serial load is selected for flag-offset-register programming, FS1/SEN is used as an enable synchronous to the
low-to-high transition of CLKA. When FS1/SEN is low, a rising edge on CLKA loads the bit present on FS0/SD into
the X-and Y-offset registers. The number of bit writes required to program the offset registers is 22. The first bit write
stores the Y-register MSB and the last bit write stores the X-register LSB.
Input-ready flag. IR is synchronized to the low-to-high transition of CLKA. When IR is low, the FIFO is full and writes
IR
O to its array are disabled. When the FIFO is in retransmit mode, IR indicates when the memory has been filled to the
point of the retransmit data and prevents further writes. IR is set low during reset and is set high after reset.
MBA
I
Port-A mailbox select. A high level on MBA chooses a mailbox register for a port-A read or write operation.
MBB
Port-B mailbox select. A high level on MBB chooses a mailbox register for a port-B read or write operation. When the
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B0–B35 outputs are active, a high level on MBB selects data from the mail1 register for output and a low level selects
FIFO data for output.
MBF1
Mail1 register flag. MBF1 is set low by the low-to-high transition of CLKA that writes data to the mail1 register. MBF1
O is set high by a low-to-high transition of CLKB when a port-B read is selected and MBB is high. MBF1 is set high by
a reset.
MBF2
Mail2 register flag. MBF2 is set low by the low-to-high transition of CLKB that writes data to the mail2 register. MBF2
O is set high by a low-to-high transition of CLKA when a port-A read is selected and MBA is high. MBF2 is set high by
a reset.
Output-ready flag. OR is synchronized to the low-to-high transition of CLKB. When OR is low, the FIFO is empty and
OR
O reads are disabled. Ready data is present in the output register of the FIFO when OR is high. OR is forced low during
the reset and goes high on the third low-to-high transition of CLKB after a word is loaded to empty memory.
RFM
Read from mark. When the FIFO is in retransmit mode, a high on RFM enables a low-to-high transition of CLKB to
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reset the read pointer to the beginning retransmit location and output the first selected retransmit data.
RST
I
Reset. To reset the device, four low-to-high transitions of CLKA and four low-to-high transitions of CLKB must occur
while RST is low. The low-to-high transition of RST latches the status of FS0 and FS1 for AF and AE offset selection.
RTM
Retransmit mode. When RTM is high and valid data is present in the FIFO output register (OR is high), a low-to-high
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transition of CLKB selects the data for the beginning of a retransmit and puts the FIFO in retransmit mode. The selected
word remains the initial retransmit point until a low-to-high transition of CLKB occurs while RTM is low, taking the FIFO
out of retransmit mode.
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