SN74ALVC3631_07 Datasheet, PDF (16/29 Pages) Texas Instruments – SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES

SN74ALVC3631, SN74ALVC3641, SN74ALVC3651
512 × 36, 1024 × 36, 2048 × 36
SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SDMS025B – OCTOBER 1999 – REVISED JUNE 2000
CLKA
ÎÎÎÎÎÎÎÎÎÎ ÌÌÌÌÌÌÌÌ _ENA
tsu(EN)
th(EN)
tsk(2)†
CLKB
1
2
tpd(C-AE)
tpd(C-AE)
AE X Words in FIFO
ENB
(X + 1) Words in FIFO
ÎÎÎÎÎÎÎÎ ÌÌÌÌÌÌÌÌÌÌ ^tsu(EN)
th(EN)
† _{tsk(2) is the minimum time between a rising CLKA edge and a rising CLKB edge for AE to transition high in the next CLKB cycle. If the time}
between the rising CLKA edge and rising CLKB edge is less than tsk(2), then AE can transition high one CLKB cycle later than shown.
NOTE A: FIFO write (CSA = L, W/RA = H, MBA = L), FIFO read (CSB = L, W/RB = H, MBB = L)
Figure 8. Timing for AE When FIFO Is Almost Empty
tsk(2)‡
CLKA
1
ÎÎÎÎÎÌÌÌÌÌ ^ENA
tsu(EN)
th(EN)
tpd(C-AF)
AF [D§ – (Y + 1)] Words in FIFO
(D§ – Y) Words in FIFO
2
tpd(C-AF)
CLKB
ENB
ÎÎÎÎÎ ÌÌÌÌ ^tsu(EN)
th(EN)
‡ _{tsk(2) is the minimum time between a rising CLKA edge and a rising CLKB edge for AF to transition high in the next CLKA cycle. If the time}
between the rising CLKB edge and rising CLKA edge is less than tsk(2), then AF can transition high one CLKA cycle later than shown.
§ _{D = 512 for the SN74ALVC3631; D = 1024 for the SN74ALVC3641; D = 2048 for the SN74ALVC3651.}
NOTE A: FIFO write (CSA = L, W/RA = H, MBA = L), FIFO read (CSB = L, W/RB = H, MBB = L)
Figure 9. Timing for AF When FIFO Is Almost Full
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