SN74ALVC3631_07 Datasheet, PDF (12/29 Pages) Texas Instruments – SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES

SN74ALVC3631, SN74ALVC3641, SN74ALVC3651
512 × 36, 1024 × 36, 2048 × 36
SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SDMS025B – OCTOBER 1999 – REVISED JUNE 2000
CLKA
4
RST
tsu(FS)
ÌÌÌ ^{FS1, FS0}
ÎÎ^th(Î^FS)ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tpd(C-IR)
IR
ENA
A0–A35
ÎÎÏÏÎÎÏÏÎÎÏÏÎÎÏÏÎÎÏÏÎÎÏÏÎÎÏÏÎÎÏÏÎÎÏÏÎÎÏÏÎÎÏÏÎÎÏÏÎÎÏÏ_tsuÎÎÏÏ_(D)AÎÎÏÏ_FOÏÏ_{ffseÏÏÏÏt} ^tst_{ÏÏÏÏ}^uh((EDN)_{ÏÏÏÏ}^)AEÏÏ_OffsÏÏÏÏ_et ÏÏÏÏ^tFhi(rÏÏÏÏ^EsNtW)ÏÏÏÏ_ordÌÌÏÏ_StoÌÌÏÏ_rediÌÌÏÏ_nFIÌÌÏÏ_FO ÌÌÏÏ
(Y)
(X)
NOTE A: CSA = L, W/RA = H, MBA = L. It is not necessary to program offset register on consecutive clock cycles.
Figure 2. Programming the AF Flag and AE Flag Offset Values From Port A
CLKA
4
RST
tpd(C-IR)
IR
tsu(FS)
ÎÎÎ FS1/SEN
ÎÎÎ _tsu(FS)
ÎÎÎÎÎÎ _FS0/SD
th(SP)
tsu(SEN)
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏÎÎÏÏÎÎÏÏÎÎÏÏÎÎÏÏÎÎÏÏÎÎÏÏÎÎÏÏÎÎ ^{th(FS) tsu(SD)}
th(SEN)
th(SD)
tsu(SEN)
tsu(SD)
th(SEN)
th(SD)
AF Offset
AE Offset
(Y) MSB
(X) LSB
NOTE A: It is not necessary to program offset-register bits on consecutive clock cycles. FIFO write attempts are ignored until IR is set high.
Figure 3. Programming the AF Flag and AE Flag Offset Values Serially
12
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265