SN74ALVC3631_07 Datasheet, PDF (11/29 Pages) Texas Instruments – SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES

SN74ALVC3631, SN74ALVC3641, SN74ALVC3651
512 × 36, 1024 × 36, 2048 × 36
SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SDMS025B – OCTOBER 1999 – REVISED JUNE 2000
mailbox registers
Two 36-bit bypass registers pass command and control information between port A and port B. The
mailbox-select (MBA, MBB) inputs choose between a mail register and a FIFO for a port data-transfer operation.
A low-to-high transition on CLKA writes A0–A35 data to the mail1 register when a port-A write is selected by
CSA, W/RA, and ENA with MBA high. A low-to-high transition on CLKB writes B0–B35 data to the mail2 register
when a port-B write is selected by CSB, W/RB, and ENB with MBB high. Writing data to a mail register sets its
corresponding flag (MBF1 or MBF2) low. Attempted writes to a mail register are ignored while its mail flag is
low.
When the port-B data (B0–B35) outputs are active, the data on the bus comes from the FIFO output register
when the MBB input is low and from the mail1 register when MBB is high. Mail2 data always is present on the
port-A data (A0–A35) outputs when they are active. The mail1 register flag (MBF1) is set high by a low-to-high
transition on CLKB when a port-B read is selected by CSB, W/RB, and ENB with MBB high. The mail2 register
flag (MBF2) is set high by a low-to-high transition on CLKA when a port-A read is selected by CSA, W/RA, and
ENA with MBA high. The data in a mail register remains intact after it is read and changes only when new data
is written to the register.
CLKA
CLKB
th(RS)
tsu(RS)
tsu(FS)
th(FS)
RST
FSM1M,BBFOFAASFI1RREF02,_{ÎÎÌÌÌÌÌÌÏÏÎÎÎÎÌÌÎÎÌÌÏÏÌÌtttpppÎÎÌÌÎÎÌÌÏÏÌÌddd(((RRRÎÎÌÌÎÎÌÌÏÏÌÌ---FFF))) ÎÎÌÌÎÎÌÌÏÏÌÌÎÎÌÌÎÎÌÌÏÏÌÌtÎÎÌÌÎÎÌÌÏÏÌÌpd(CÌÌÏÏÌÌ-IR)ÌÌÏÏÌÌÌÌÏÏÌÌÌÌÏÏÌÌtpdÌÌÏÏÌÌ(C-O}ÏÏÌÌ_R)ÏÏÌÌÏÏÌÌÏÏÌÌÏÏ 0,1ÏÏÏÏÏÏÏÏ_tpdÏÏ_(C-IÏÏ_R) ÏÏÏÏÏÏÏÏÏÏÏÏ
Figure 1. FIFO Reset Loading X and Y With a Preset Value of Eight
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